MC145574APB Freescale Semiconductor, MC145574APB Datasheet

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ISDN S/T-Interface Transceiver MC145574 Coming through loud and clear. m MC145574/D REV 6 ...

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MC145574 ISDN S/T-Interface Transceiver Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...

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MC145574 TABLE OF CONTENTS MC145574 ISDN S/T-INTERFACE TRANSCEIVER 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 TABLE OF CONTENTS 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 TABLE OF CONTENTS 6.5.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 TABLE OF CONTENTS 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 TABLE OF CONTENTS 11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 TABLE OF CONTENTS 15.5 IRQ3 NR3(3) — CHANGE IN Rx INFO STATE NR4(3) — ENABLE 15.6 IRQ6 NR3(1) — NT: FAR–END CODE VIOLATION (FECV) DETECTION TE: NOT APPLICABLE NR4(1) — ENABLE 15.7 GCI MODE . . . . . ...

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MC145574 TABLE OF CONTENTS 19.1 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 LIST OF FIGURES Figure 1–1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MC145574 LIST OF TABLES Table 3–1. NT Mode Transmission States Table 3–2. TE Mode Transmission States Table 4–1. IDL2 Clock Speeds Table 6–1. CLK1, CLK0 GCI Clock Selection Table 6–2. GCI Timeslot Assignment Table 6–3. M2, M1, and M0 Pins ...

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Contents–x MC145574 MOTOROLA ...

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INTRODUCTION The MC145574 is Motorola’s second generation S/T transceiver and is a follow–up to the MC145474/75 transceiver. The MC145574 provides the improved interfacing capabilities and reduced power consumption re- quired by today’s ISDN applications, while maintaining the functionality and ...

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Section 7 contains pin descriptions of the MC145574. The pin descriptions differentiate between the device configured for NT mode or TE mode of operation, and GCI and IDL2+SCP. As mentioned previously, the MC145574 is used for the transmission of two ...

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BLOCK DIAGRAM TxP TxN ISET Tx MODULATOR 2B+D EXTALOUT XTALIN 1.5 PACKAGING The MC145574 comes in the following packages: 28–Pin, 600 mil Wide, Plastic SOIC 32–Pin, 700 mil Square, TQFP The pin assignments for the MC145574 are described in ...

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MC145574 MOTOROLA ...

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INTRODUCTION The MC145574 ISDN S/T transceiver conforms to CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications layer 1 transceiver designed for use at the ISDN S and T reference points designed for both ...

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SHORT PASSIVE BUS OPERATION The short passive bus is intended for use when up to eight TEs are required to communicate with one NT. The TEs can be distributed at any point along the passive bus, the only requirement ...

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The essence of this configuration is that a restriction is placed on the distance between the TEs. The distance, D3 (as shown in Figure 2–3), corresponds to the maximum distance between the grouping of TEs. CCITT I.430, ETSI ETS 300012, ...

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MC145574 MOTOROLA ...

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ACTIVATION/DEACTIVATION OF S/T TRANSCEIVER 3.1 INTRODUCTION CCITT I.430, ETSI ETS 300012, and ANSI T1.605 define five information states for the S/T transceiver. When the the fully operational state, it transmits INFO 4. When the ...

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ACTIVATION OF S/T LOOP BY TE The TE activates an inactive loop by transmitting INFO 1 to the NT. This is accomplished in the MC145574 by setting NR2( Note that this bit is internally reset to ...

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DEACTIVATION PROCEDURES CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications dictate that only an NT can deactivate the S/T loop. Intuitively, this has to be the case because in a passive bus if one TE sends INFO 0, ...

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A Bit An S/T frame consists of 48 bauds. In the direction, one of these bauds is for the A bit. The A bit is set to 1 when the S/T loop is in the fully ...

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INTRODUCTION The Interchip Digital Link (IDL2) of the MC145574 is backwards compatible with the IDL of the MC145474/75 S/T transceiver of first generation. In addition to the standard operating mode, this en- hanced interface features new modes that are ...

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D in This pin is always an input. Data to be output on the S/T–interface is input on this pin. D out This pin is a three–state output. Data received on the S/T–interface is output on this pin during pro- ...

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NT IDL2 Master As mentioned previously, the normal configuration for the MC145574, when configured IDL2 slave. However, in order to facilitate testing of the environment in which the MC145574 resides, the capability exists ...

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Additional Notes 4.3.6.1 Phase Relationship of the NT Transmit Signal with Respect to FSC/FSR The MC145574 operating behaves as an IDL2 slave, FSC/FSR and DCL being inputs to the device. FSC/FSR is a single positive polarity ...

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FSC/FSR TRANSMIT (INFO ...

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RECEIVED SIGNAL (INFO TRANSMITTED SIGNAL (INFO 3) 2 BAUD TURNAROUND – 10 ...

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FSC/FSR TRANSMIT (INFO ...

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NT S SYNC NT S SYNC NT S SYNC NT S SYNC SUBSCRIBER LINES S–INTERFACE Independent timeslot assignment is available for the B1, B2, and D channels in both the transmit and receive directions. B1, B2, and D timeslots may ...

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TSEN Signal The TSEN signal is enabled via the SCP. See description for OR7 bits 1 and 0. This pin then becomes an open drain output that pulls low when data is being output from D out . This ...

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FSC/FSR DCL out FSC/FSR DCL out Figure 4–6. Standard IDL2 8–Bit Mode with Long Frame Sync FSC/FSR DCL D in ...

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Figure 4–8. Timeslot Operation with Independent Slave Frame Syncs, TSEN MOTOROLA Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü Ü ...

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MC145574 MOTOROLA ...

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INTRODUCTION The MC145574 is equipped with a serial control port (SCP). This SCP is used by external devices (such as an MC145488 DDLC or 68302) to communicate with the S/T transceiver. The SCP is an industry standard serial control ...

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SCPCLK is encountered. Note that SCP Rx is ignored during the time that SCP Tx is being driven. Also note that SCP Tx comes out of high impedance only when ...

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SCP Byte Register Read A byte register read is a 16–bit SCP transaction. Figure 5–3 illustrates this process. To initiate an SCP byte register read, the SCPEN is brought low. Following this, an R/W bit is shifted in from ...

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SCPEN SCPCLK DON’T CARE SCP Rx R/W HIGH IMPEDANCE SCP Tx Figure 5–4. Serial Control Port Byte Register Read Operation Double 8–Bit Transaction 5.2.4 SCP Byte Register Write A byte register write is also a 16–bit SCP transaction. Figure 5–5 ...

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When SCPEN comes low again, the next eight rising edges of SCPCLK shift data in from SCP Rx. This data is then stored in the selected byte. Figure 5–6 illustrates this process. SCPEN SCPCLK DON’T CARE SCP Rx R/W SCP ...

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SIGNAL DESCRIPTION There are five signals which constitute the SCP bus. 1. SCP Tx 2. SCP Rx 3. SCPCLK 4. SCPEN 5. IRQ A description of each signal follows. 5.3.1 SCP Tx SCP Tx is used to output control, ...

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SCPEN This signal, when held low, selects the SCP for the transfer of control, status, and data information into and out of the MC145574 S/T transceiver. SCPEN should be held low for periods of the SCPCLK ...

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MC145574 MOTOROLA ...

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OVERVIEW The MC145574 is able to work with a General Circuit Interface port (GCI). The GCI is a standard four–wire interface between devices for the subscriber access in ISDN and analog environments. The principle use in these applications is ...

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FSC DCL out FSC DCL D out CH0 D in Figure 6–1a. Relative Channel Positions (GCI Slave Mode) 6–2 125 s ...

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FSC DCL D out FSC DCL D out D in FSC DCL D out CH0 D in Figure 6–1b. Relative Channel Positions ...

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GCI INDIRECT MODE When control of the SCP interface is available, a pseudo GCI mode can be activated through the GCI control register. In the indirect mode, the SCP interface operates as normal and the IDL2 interface operates in ...

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S(2:0), OR5(b2, b1, b0) These three bits select the GCI timeslot that the device will use. S(2:0)=0 is the default state, timeslot 0. The timeslot selected must be compatible with the DCL clock rate being used (i.e., if the clock ...

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GCI DIRECT MODE The alternative GCI mode is direct mode. This mode should be used when a fully–compliant GCI is required. In this mode, the SCP interface is not available GCI direct mode the monitor, C/I, and ...

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In the GCI NT master mode possible to select both NT1 Star and NT Terminal modes via the Monitor channel. The associated pins used in the default IDL2 mode are enabled and operate in the same manner. Table ...

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Monitor Channel Operation The Monitor channel is used to access the internal registers of the MC145574. All Monitor channel messages are two bytes in length. Each byte is sent twice to permit the receiving GCI device to verify data ...

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FSC 125 s NULL E BYTE1 E BYTE1 out E BYTE2 E BYTE2 E NULL ...

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Monitor Channel Commands A GCI device transmits Monitor channel commands to a receiving MC145574 to access its internal register set. The receiving MC145574 then transmits a Monitor channel response message onto the Monitor channel for commands that request data ...

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Accessible Monitor Channel Registers The following register maps indicate the internal SCP registers that are accessible via the Monitor channel. Items that are in bold print indicate functions that are different to those of the SCP version. See Sections ...

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BR15 Overlay Register Enabled (7) (6) OR6 TSA B1 TSA B2 Enable Enable OR7 Disable 3 V Enable Regulator S/G Bit OR8 OR9 NT TE OR15 Overlay Register Enable All these registers are detailed in the following sections ...

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Table 6–8. C/I Channel Commands and Indications TE Master C/I C/I Code Indication Command 0000 DR 0001 — 0010 — 0011 — 0100 RSY 0101 — 0110 — T1/T3EXP 0111 — 1000 AR 1001 — 1010 — 1011 — AREOM ...

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GCI ACTIVATION AND DEACTIVATION TIMING DIAGRAMS The following diagrams (Figures 6–4 through 6–6) indicate the flow of the activation/deactivation proce- dure and are not intended to be exhaustive in all the possible permutations ...

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AI AR8, AR10 MOTOROLA TEM INFO INFO INFO INFO Figure 6–5. Deactivation from NT End TEM INFO INFO ...

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MC145574 MOTOROLA ...

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INTRODUCTION The Motorola MC145574 ISDN S/T transceiver is available in a 28–pin SOIC and a 32–pin TQFP package (see Figure 7–1). 28–LEAD SOIC ISET 1 RxN 2 RxP 3 TE/NT 4 M/S 5 T_IN/TFSC/TCLK/FIX SG/DGRANT/ANDOUT ...

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TE/NT This pin allows the external selection mode. When this pin is held low, the NT mode is selected; and when it is held high, the TE mode is selected. This pin is OR’d with ...

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CLASS/ECHO_IN This pin performs two functions dependent on the mode of operation. In the NT1 Star mode the ECHO_IN input function for use in NT1 Star applications. In the TE master mode, this pin is the class ...

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In IDL2 mode, this pin can also be used as the 8 kHz frame sync (FST) for the transmit path. In this mode, the pin is bidirectional, the direction depending on whether the device is an IDL2 master or slave. ...

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MC145574 should be reset. This pin is a Schmitt–trigger input and could have an external RC circuit connected to perform the power–on reset function. 7.3 ADDITIONAL NOTES 7.3.1 Input Levels The MC145574 S/T transceiver is always TTL/CMOS ...

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MC145574 MOTOROLA ...

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NIBBLE REGISTER MAP DEFINITION 8.1 INTRODUCTION There are seven nibble registers (NR0 through NR6) in the MC145574. Control and status information reside in these nibble registers, which are accessed via the SCP. For a detailed description of access procedures, refer ...

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Table 8–3. Nibble Register Initialization After Any Reset IDL TE NR0 0 NR1 0 NR2 0 NR3 8 NR4 0 NR5 0 NR6 0 NOTE: All values in hexadecimal unless shown otherwise. 8.2 NR0 This register is a read/write register ...

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NR1 This register is a read only register and can be reset by application of either a hardware or software reset. A per–bit description of nibble register 1 (NR1) follows. NR1 Activation Indication NR1(3) — Activation Indication (AI) This ...

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This action indicates that the requested action has been recognized. Note that NR2( read/write bit. NR2(2) — NT: Deactivate Request DR TE: Not Applicable ...

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INFO 1, INFO 3, or INFO X state. Alternatively, in the TE mode, this corresponds to a change in the receiving INFO 0, INFO 2, INFO 4, or INFO X state. Thus, when a change occurs in one of these ...

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NR4(3) — Enable IRQ3 NR4( interrupt mask bit for IRQ3. When this bit is set high and IRQ3 is pending (i.e., NR3(3) having been internally set to a 1), an interrupt is given to an external device by ...

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This function may be used in multidrop configurations or in applications where the output B channel transmission must be held in the “idle 1s” condition. Note that NR5( read/write bit in the TE mode. NR5(2) NT: Idle B2 ...

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NR6(0) – Swap B1 and B2 When NR6( the timeslot assigned positions of the B1 and B2 channel data input and output via the IDL2 interface functions normally. When NR6(0) is set to 1, the timeslot positions of ...

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BYTE REGISTER MAP DESCRIPTION 9.1 INTRODUCTION There are 16 byte registers (BR0 through BR15) in the MC145574. Control, status, and maintenance information reside in these byte registers, which are accessed via the SCP. For a detailed description of access procedures, ...

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Table 9–2. Byte Register Map for TE Mode of Operation (7) (6) BR2 Q.1 Q.2 BR3 SC1.1 SC1.2 BR4 FV7 FV6 BR5 BPV7 BPV6 BR6 B1 S/T B1 S/T Loopback Loopback Transparent Non– Transparent BR7 Activation D Channel Procedures Procedures ...

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BR0 The functions that were related to the IDL2 M FIFO of the MC145474 have been removed; writing to this register has no effect, and reading it returns FFH. (No register shown.) 9.3 BR1 The functions that were related ...

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Note that BR3(7) is the MSB of the received Q channel nibble, and BR3(4) is the LSB. Refer to Section 12 for a more detailed description of this feature. Reading BR3 ...

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BR5 (7) BR5 BPV7 BPV6 BR5(7:0) is the output of an 8–bit binary counter. This counter counts the number of unbalanced frames. A frame in which the total number of positive pulses is different from the total number of ...

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B2 timeslot is ignored. IDL2 Tx ignores the demodulated B2 data, presenting in its stead the “idle 1s” condition in the IDL2 Rx B2 timeslot (hence, the term “non–transparent”). This bit is reset either a software reset, ...

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Note that if activation procedures are disabled as a TE, causing INFO transmitted, then this state may or may not be commensurate with receiving INFO 0 from the NT. In the event that INFO 0 is being ...

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If the loop is active, these signals will be synchro- nous to the inbound data. This bit is a read/write bit and is reset application of either a software ...

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BR9(7:4) NT: SC2 to Loop — BR9(7:4) is used for multiframing. In the NT mode of operation, these four bits correspond to subchannel 2 for transmission to the TE(s). Multiframing is initiated by the NT by setting BR7(5). When multiframing ...

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Note that BR10(7) is the MSB of SC4 and BR10(4) is the LSB. Refer to Section 10 multiframing for a detailed description of the multiframing procedure. TE: ...

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BR11(5), BR11(4) — Rx INFO State B1 and B0 These bits are read/write bits and are applicable to both NT and TE modes of operation. The MC145574 internally sets these bits to indicate the status of the received signal; i.e., ...

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BR11(0) — Transmit 96 kHz Test Signal This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit is 0, the MC145574 functions normally. When this bit is 1, the device ...

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Refer to Section 11 for a detailed description of this mode. Application of a hardware or software reset resets this bit to 0. BR13(2) — NT: Force Echo Channel to Zero TE: Not Applicable This bit is a read/write bit ...

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MC145574 MOTOROLA ...

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OVERLAY REGISTER MAP DEFINITION 10.1 INTRODUCTION There are eleven overlay registers (OR0 through OR9 and OR15) in the MC145574. The overlay regis- ters are a second bank of registers available when the overlay register control bit BR15(7) is set to ...

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Table 10–2. Overlay Register Initialization After Any Reset IDL TE OR0 00 OR1 04 OR2 08 OR3 00 OR4 04 OR5 08 OR6 00 OR7 00 OR8 00 OR15 00XX XXXX NOTES: 1. All values in hexadecimal unless shown otherwise. ...

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OR3 (7) OR3 OR3(7:0) — Channel Timeslot This register allows the B1 channel timeslot output from the D out pin to be allocated 1 of 256 start points, corresponding to each 2–bit boundary defined by the CLK. ...

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OR6 (7) OR6 TSA B1 Enable OR6(7) — Control Register, TSA B1 Enable This bit is used to enable the B1 channel in IDL2 timeslot mode. The B1 timeslot is defined through the OR0 and OR3 registers. Whenever any ...

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OR7 (7) OR7 Disable Enable 3 V S/G Bit Regulator OR7(7) — Control Register, Disable 3 V Regulator This bit can be used to disable the supply regulator and allow three volts to be driven from an external supply. ...

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TSEN D channel signal can be enabled only if TSEN B1/B2 channel signals are enabled (OR7(1) = 1). 10.10 OR8 (7) OR8 Reserved OR8(7) — Reserved This bit is reserved. OR8(6) — Reserved ...

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OR9 (7) OR9 OR9(2) — Control Register, Force INFO 2 Transmission When the device is initialized, this bit is logic 0. When set to a logic 0, the device operates as normal in all modes. This register bit is ...

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MC145574 MOTOROLA ...

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INTRODUCTION The S/T–interface is designed for full–duplex transmission of two 64 kbps B channels and one 16 kbps D channel between one NT device and one or more TEs. The TEs gain access to the B channels by sending ...

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IDL2 D CHANNEL OPERATION 11.2.1 Gaining Access to the D Channel in the TE Mode The pins DREQUEST and DGRANT are used in the TE mode of operation to request and grant access to the D channel. An external ...

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Generation of an Interrupt in the TE Mode The MC145574 in the TE mode of operation generates an interrupt every time a collision occurs on the D channel. CCITT I.430, ETSI ETS 300012, and ANSI T1.605 define a collision ...

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FSC D out D in 11– CH0 CH1 SCIT TERMINAL MODE, DCL = 1536 kHz Figure 11–1. SCIT Terminal Mode MC145574 S/G BIT CH2 MOTOROLA ...

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INTRODUCTION A layer 1 signalling channel between the NT and TE is provided in the MC145574 in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. In the NT and TE direction, this layer 1 channel is the ...

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Frame No 12.4 MULTIFRAME INTERRUPTS IN AN NT-CONFIGURED MC145574 The NT will generate an interrupt either once every ...

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READING Q CHANNEL DATA FROM AN NT-CONFIGURED MC145574 The Q data nibble received from the TE(s) is obtained by reading BR3(7:4). The demodulated Q chan- nel data is written to this register every 5 ms. BR3(7:4) are read only ...

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MC145574 MOTOROLA ...

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The MC145574 can be configured in several different modes for different applications. The following sections describe the various configurations available for the NT and TE modes. 13.1 NT CONFIGURATIONS To select NT mode, the TE/NT pin must be held low. ...

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In slave mode, the IDL2/GCI interface frame sync and clock are inputs, and the S/T loop interface timing is slaved to these inputs. In master mode, the IDL2/GCI interface frame sync and clock are outputs; these signals being derived from ...

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V FSC DCL out MOTOROLA + 5 V ANDIN ANDOUT ECHOIN FSC DCL out ANDIN ANDOUT ECHOIN FSC DCL out ANDIN ANDOUT ECHOIN FSC DCL out ...

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NT Terminal Mode In NT Terminal mode, another IDL2 channel data port is opened on the device. This port has four pins associated with it. They are DREQUEST, DGRANT, CLASS, and T_IN. This port has the capability of competing ...

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TE Master Mode (TEM) The TEM mode is the normal mode of operation for a TE. The two main operational features of TEM mode are as follows. The IDL2/GCI is a master of the digital interface. This means that ...

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An example architecture of an NT2 is shown in Figure 13–3. The TFSC signal supplied by the TE in slave mode is used via a clocksource selector to synchronize the whole NT2 to the network SYNC NT S ...

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Figure 14–1 shows the recommended crystal oscillator for connection to the MC145574. XTAL EXTAL Figure 14–2 shows the connection when using an external clock. XTAL EXTAL MOTOROLA Figure 14–1. Typical ...

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MC145574 MOTOROLA ...

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INTRODUCTION When the MC145574 in SCP is configured as a TE, it has three interrupt modes. When the MC145574 is configured as an NT, it has four interrupt modes. Each of these interrupts is maskable. When an interrupt occurs ...

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BR3(7:4). Similarly, data to be transmitted in the Q channel of the TE is internally latched from BR2(7:4) during the 47th baud of the transmitted INFO 3 in the 20th frame of a multiframe. At this ...

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TRANSMISSION LINE INTERFACE CIRCUITRY 16.1 INTRODUCTION The MC145574 is an ISDN S/T transceiver fully compliant with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. As such designed to interface with a four–wire transmission medium, one pair being the ...

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MC145574 MC145574 NOTES: 1. Diodes are 1N4148 or MMAD1108. 2. The MMAD1108 is a monolithic array of eight diodes and is a Motorola preferred device. 3. All resistors are 1/4 watt. 16– THESE FOUR DIODES ARE OPTIONAL IN ...

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ADDITIONAL NOTES 16.4.1 Sources of Line Interface Transformers Line interface transformers for use with the MC145574 S/T may be obtained from the following manufacturers: Pulse Engineering P.O. Box 12235 San Diego, California 92112 Tel : 619–674–8100 Fax : 619–674–8262 ...

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MC145574 MOTOROLA ...

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POWER SUPPLY STRATEGY The MC145574 operates from This regulator has an output of 3.2 V. This regulated 3 V supply powers all of the internal digital logic, resulting in reduced power consumption. The analog receiver/transmitter blocks ...

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Absolute Minimum Power In this mode, the device is forced into the absolute minimum power state from which it cannot be activated from the S/T–interface. All internal circuits are disabled, including the XTAL oscillator, and only the SCP interface ...

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MAXIMUM RATINGS This device contains circuitry to protect the inputs against damage due to high static voltages or electri- cal fields; however advised that normal precautions be taken to avoid applications of any voltage higher than maximum ...

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ANALOG CHARACTERISTICS ( – 5.0 V TxP/TxN Drive Current (TxP – TxN) Voltage Limit Rx Input Sensitivity, Normal Mode (RxP – RxN) Rx Input Sensitivity, ...

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IDL2 TIMING CHARACTERISTICS 18.5.1 IDL2 Master Timing, 8- and 10-Bit Formats Ref. No. 1 FSC Period 2 Delay From the Rising Edge of DCL to the Rising Edge of FSC 3 Delay From the Rising Edge of DCL to ...

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IDL2 Slave Timing, 8- and 10-Bit Formats Ref. No. 14 FSC Period 15 FSC High Before the Falling Edge of DCL (FSC Setup Time) 16 FSC High After the Falling Edge of DCL (FSC Hold Time) 17 Delay From ...

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Figure 18–2. IDL2 Slave Timing, 8– and 10–Bit Formats MOTOROLA MC145574 18–5 ...

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GCI TIMING FOR MASTER AND SLAVE MODE Ref. No. 1 Delay From Rising Edge of DCL to FSC Output High 2 Delay From Rising Edge of DCL to FSC Output Low 3 FSC Input High Before the Falling Edge ...

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Figure 18–3. GCI Timing For Master and Slave Mode MOTOROLA MC145574 18–7 ...

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SCP TIMING CHARACTERISTICS ( – 5.0 V Ref. No. 12 SCPEN Active Before Rising Edge of SCPCLK 13 SCP Rising Edge Before SCPEN Active 14 SCP Rx Valid Before ...

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NT1 STAR MODE TIMING CHARACTERISTICS Ref. No. 25 Propagation Delay from ANDIN to ANDOUT 18.9 D CHANNEL TIMING CHARACTERISTICS (IDL2 MODE) Ref. No. 26 DREQUEST Valid Before Falling Edge of FSC 27 DREQUEST Valid After Falling Edge of FSC ...

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PIN ASSIGNMENTS MOTOROLA MECHANICAL DATA ISET 1 28 RESET RxN 2 27 TxP RxP 3 26 TxN TE/ XTAL M EXTAL T_IN/TFSC/TCLK/FIX I/O SG/DGRANT/ANDOUT ...

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PACKAGE DIMENSIONS –A– 28X 0.010 (0.25 26X 19–2 DW SUFFIX SOIC CASE 751F– 14X 0.010 (0.25) B –B– –T– SEATING ...

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–T– –AB– SEATING –AC– PLANE DETAIL AD MOTOROLA PB SUFFIX TQFP CASE 873A– 0.20 (0.008) AB T– –U– V DETAIL ...

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FUNCTIONAL DIFFERENCES This section refers to MC145574 S/T–interfaces marked F57F4 and with a revision number BR15 = 03. This mask set of the MC145574 has some functional differences from what is presented in this data book. 20.1.1 Differences in ...

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MC145574EVK ISDN S/T-INTERFACE A.1 INTRODUCTION The MC145574EVK S/T–Interface Transceiver Evaluation Kit provides Motorola ISDN customers a convenient and efficient vehicle for evaluation of the MC145574 ISDN S/T–Interface Transceiver. The approach taken to demonstrate the MC145574 S/T–Interface Transceiver is to provide ...

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A.2 FEATURES A.2.1 General Provides Standalone NT and Single Board On–Board 68HC11 Microcontroller With Resident Monitor Software Convenient Access to Key Signals NT and TE Software Development Platform A.2.2 Hardware Only + 5 Volt Power Supply Gated ...

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A.3 BLOCK DIAGRAM EIA–232 SCP MC68HC11E9 MICROCONTROLLER IDL S/T–INTERFACE TRANSCEIVER LINE ANALOG INTERFACE MOTOROLA MC145407 XC3020A SCP IDL MC145574 ISDN S/T Figure A–2. Block Diagram MC145574 PROM BERT CLK XILINX IDL MC145574 ISDN S/T–INTERFACE TRANSCEIVER LINE ANALOG INTERFACE S/T A–3 ...

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A–4 MC145574 MOTOROLA ...

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GLOSSARY OF TERMS AND ABBREVIATIONS The list contains terms found in this and other Motorola publications concerned with Motorola Semiconductor prod- ucts for Communications. A–Law — A European companding/encoding law commonly used in PCM systems. A/B Signaling — A special ...

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CIDCW — Calling Identity Delivery on Call Waiting; a subscriber feature which allows for the display of the time, date, number, and possible other information about the caller to the called party while the called party is off–hook. CLASS — ...

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Relative power expressed in dBmp. (See dBmO and dBmp.) dBmp — Indicates dBm measurement made with a psophometric weighting filter. dBrn — Relative signal level expressed in decibels above reference noise, where reference noise is 1 pW. Hence, ...

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Half Duplex — A transmission system that permits communication in one direction at a time. CB ratios, with “push–to–talk” switches, and voice–activated speakerphones, are half duplex. Handset — A rigid assembly providing both telephone transmitter and receiver in a form ...

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NT2 — Network Termination 2 (OSI Layers 2 and 3). Off–Hook — The condition when the telephone is connected to the phone system, permitting loop current to flow. The central office detects the dc current as an indication that the ...

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Signal–to–Distortion Ratio (S/D) — The ratio of the input signal level to the level of all components that are present when the input signal (usually a 1.020 kHz sinusoid) is eliminated from the output signal (e.g., by filtering). SLIC — ...

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UDLT — Universal Digital Loop Transceiver; a Motorola originated name for a voice/data transceiver circuit. VCO — Voltage–controlled oscillator. Input is a voltage; output is a sinusoidal waveform. VCM — Voltage–controlled multivibrator. Input is a voltage; output is a square ...

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B–8 MC145574 MOTOROLA ...

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A Activation, 3–1, 3–2, 6–14, 6–15, 8–3, 9–6, 9–8 GCI, 6–14 Adaptive Timing, 13–1 ANSI T1.605, 1–2 B Byte Register, 5–3, 5–4, 9–1 Initialization, 9–2 Read, 5–3 Write, 5–4 C CCITT I.430, 1–2 CLASS, 7–3 Class, 11–2 Clock, 4–9, 7–4, ...

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L Line Interface, 16–1 Long Frame, 4–8 Loopback, 8–7, 9–5 Loopbacks, 1– and N Parameters, 3–3 Master, 4–3, 7–2, 13–1 GCI, 6–6 Monitor Channel, 6–7, 6–8, 6–11 Commands, 6–10 Messages, 6–8 Operation, 6–8 Response Messages, 6–10 Status Indication ...

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MOTOROLA AUTHORIZED DISTRIBUTOR & WORLDWIDE SALES OFFICES NORTH AMERICAN DISTRIBUTORS UNITED STATES ALABAMA Huntsville Allied Electronics, Inc Arrow Electronics ...

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FLORIDA – continued Tallahassee FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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AUTHORIZED DISTRIBUTORS – continued UNITED STATES – continued KANSAS – continued Olathe PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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NEW YORK – continued Rochester Allied Electronics, Inc Arrow Electronics . . . . . . . . . ...

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AUTHORIZED DISTRIBUTORS – continued UNITED STATES – continued PENNSYLVANIA Allentown Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CANADA ALBERTA Calgary FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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INTERNATIONAL DISTRIBUTORS ARGENTINA Electrocomponentes . . . . . . . . . . . . . . . . . . . . . (5–41) 375–3366 Elko . . . . . . . . . . . . ...

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NORWAY Arrow Tahonic A A/S Avnet EMG . . . . . . . . . ...

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MOTOROLA WORLDWIDE SALES OFFICES UNITED STATES ALABAMA Huntsville . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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PHILIPPINES Manila . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Paranaque . . . ...

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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 Mfax™: Motorola Fax Back System RMFAX0@email.sps.mot.com – Touchtone 1-602-244-6609 – US & Canada ONLY 1-800-774-1848 – http://sps.motorola.com/mfax/ Home Page: http://motorola.com/sps/ Mfax ...