MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 80

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

or software reset sets these bits to all 1s. Note that BR3(7) is the MSB of the received Q channel
nibble, and BR3(4) is the LSB. Refer to Section 12 for a more detailed description of this feature.
Reading BR3 clears the multiframe interrupt.
TE: SC1 FROM S/T LOOP — BR3(7:4) are used in the multiframing mode of operation. When the
device is configured as a TE and multiframing has been enabled, these bits correspond to the received
subchannel 1 nibble from the NT. These bits are updated once every multiframe. The TE–configured
device can give an interrupt once every multiframe, or every time a new subchannel nibble (SC1)
is received (see BR3(2) and NR4(2)). BR3(7:4) are read only bits. Application of either a hardware
or software reset resets these bits to all 0s. Note that BR3(7) is the MSB of the received SC1 subchannel
nibble and BR3(4) is the LSB. Refer to Section 12 for a more detailed description of this feature.
BR3(3) — NT: Q Bit Quality Indicate
TE: Not Applicable
In the NT mode, this bit corresponds to the Q bit quality indication. When multiframing has been initiated
by the NT, the TE(s) will respond by sending Q data once every five frames. This Q data will be trans-
mitted in the Fa bit position. During the other four frames (i.e., when the TE(s) are not transmitting
Q data), the Fa bit should be a 0. BR3(3) being high indicates that the Fa bits in the frames where
multiframing data was not being transmitted were 0s. This bit is a read only bit and is reset to 0 by
application of either a hardware or software reset.
BR3(2)
NT: Interrupt Every Multiframe — Programming of BR3(2) dictates whether an interrupt will be given
every multiframe (assuming multiframing has been enabled and IRQ2 enable, NR4(2), has been set),
or only on the receipt of a new Q channel nibble from the TE(s). When BR3(2) is 1, an interrupt is
given every multiframe. When BR3(2) is 0, an interrupt is given only on the receipt of a new Q channel
nibble. Refer to Section 12 for a more detailed description. BR3(2) is a read/write bit and is reset
to 0 by application of either a hardware or software reset.
TE: Interrupt Every Multiframe — Programming of BR3(2) dictates whether an interrupt will be given
every multiframe (assuming multiframing has been enabled and IRQ2 enable, NR4(2), has been set),
or only on the receipt of a new SC1 subchannel nibble from the NT. When BR3(2) is 1, an interrupt
is given every multiframe. When BR3(2) is 0, an interrupt is given only on the receipt of a new SC1
subchannel nibble. Refer to Section 12 for a more detailed description. BR3(2) is a read/write bit and
is reset to 0 by application of either a hardware or software reset.
9.6
BR4
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR4
FV7
FV6
FV5
FV4
FV3
FV2
FV1
FV0
Recommendation CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications state that there
must be two AMI violations in every S/T frame. The F bit is the first violation and the succeeding violation
must occur within 13 or 14 bauds, depending on the configuration of the transceiver as either an NT
or TE. BR4(7:0) is the output of an 8–bit binary counter. This counter counts the number of frames
which do not contain the correct number of AMI violations. Note that in multiframing, it is possible
to have a frame which does not contain the correct number of violations (Fa = 1, B1 = 1). The
MC145574, when in multiframe mode, does not count these frames. Thus, this counter is a “frame
error” counter, counting the number of frames which do not contain the correct number of AMI viola-
tions. BR4(7:0) only counts frames not containing the correct number of AMI violations after FSYNC
has been achieved, and ceases counting whenever FSYNC is lost.
BR4(7:0) is applicable to both NT and TE modes of operation. It is a read/write register, thereby allowing
the user to program the counter to a predetermined value. The counter is initialized to “100” by a
hardware/software reset. Note that the counter, upon reaching a value of “FF”, will not roll over; i.e.,
it will remain at “FF” until the user rewrites a starting value. Note that BR4(7) is the MSB of the counter
and BR4(0) is the LSB.
9–4
MC145574
MOTOROLA