MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 28

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

4–2
4.3.1
4.3
D in
This pin is always an input. Data to be output on the S/T–interface is input on this pin.
D out
This pin is a three–state output. Data received on the S/T–interface is output on this pin during pro-
grammed timeslots and is high impedance at all other times.
TSEN/FST
This pin is normally three–state, but it can be reconfigured through the SCP to be used as TSEN
or FST. See Register OR7 description.
TSEN is an open drain output. TSEN can be used to enable an external bus driver and pulses low
when data is being output on the D out pin. This signal can be used to control a high drive bus/backplane
driver in applications where the D out data is going off–board. Since TSEN is open drain, it can be
wire–OR’d with other devices and share the same driver.
This pin can also be reconfigured through the SCP to be used as FST. In this mode, the IDL2 interface
operates with two independent frame syncs, one for the Tx direction (FST) and one for the Rx direction
(FSR). FST is bidirectional, the direction depending on whether the IDL2 is a master or a slave.
TFSC/TCLK/T_IN/FIX
This pin is the FIX input in NT modes, but in the TE slave mode it is reconfigured to be used as TFSC
and outputs an 8 kHz signal that is synchronized to the incoming S/T–interface frames. The TFSC
can be used in NT2 applications where the TE slave mode is utilized. The TFSC can be used to synchro-
nize the TE slaves to the network. Alternatively, this pin can output TCLK, selected via the SCP. TCLK
is a clock whose frequency can be chosen via the SCP, which is also synchronized to the received
S/T–interface. TCLK can be used as an alternative to TFSC in the NT2 slave–slave mode. Refer to
the slave–slave mode section for further details on TFSC and TCLK. See Register OR7 description.
In the NT Terminal mode (NTTERM), this pin is T_IN. See the section on NT Terminal mode. See
description for Register OR8.
IDL2 STANDARD MODE
NT IDL2 Slave
This is the normal mode of operation for the MC145574, when active as an NT. In this mode FSC
and DCL are inputs to the device, and the outgoing S/T frame is synchronized to the IDL2 frame sync.
Typically the MC145574, when configured as an NT, is situated on a line card or an NT1 box. As
an IDL2 slave, this allows the S/T chip to derive its timing from the backplane or from the
MC14LC5472/MC145572 U–chips. As mentioned previously, FSC must be 8 kHz, while DCL can be
input to the device with any frequency from 512 kHz to 4.096 MHz.
When the MC145574 is configured as an NT, then BR7(3) determines whether the NT is acting as
an IDL2 master or as an IDL2 slave. When BR7(3) is a 0, the MC145574, when acting as an NT,
is behaving as an IDL2 slave. Conversely, when BR7(3) or OR8(3) is set to a 1, or when pulling high
the M/S pin, the chip acting as an NT behaves as an IDL2 timing master.
Table 4–1. IDL2 Clock Speeds
BR13(5)
MC145574
0
0
1
1
BR7(2)
0
1
0
1
2.048 MHz
1.536 MHz
2.56 MHz
512 kHz
DCL
MOTOROLA