MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 39

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
5.2.1
5.1
5.2
INTRODUCTION
The MC145574 is equipped with a serial control port (SCP). This SCP is used by external devices
(such as an MC145488 DDLC or 68302) to communicate with the S/T transceiver. The SCP is an
industry standard serial control port and is compatible with Motorola’s SPI, which is used on several
single–chip MCUs.
The SCP is a five–wire bus with control and status bits, with data being passed to and from the S/T
transceiver in a full–duplex fashion.
The SCP interface consists of a transmit path, a receive path, an associated clock, an enable signal,
and an interrupt indicate. These signals are known as SCP Tx, SCP Rx, SCPCLK, SCPEN, and IRQ.
The clock determines the rate of exchange of data in both the transmit and receive directions, the
enable signal governs when this exchange is to take place, and the interrupt signal indicates that
an interrupt condition exists and a read operation of the interrupt status register (NR3) is required.
The operation/configuration of the S/T transceiver is programmed by setting the state of the control
bits within the S/T transceiver. The control, status, and data information reside in eight 4–bit–wide
nibble registers, sixteen 8–bit–wide byte registers, and sixteen 8–bit–wide overlay registers. The nibble
registers are accessed via an 8–bit SCP bus transaction. The 16–byte–wide registers are accessed
by first writing to a pointer register within the eight 4–bit–wide nibble registers. This pointer register
(NR(7)) then contains the address of the byte wide register to be read from or written to on the following
SCP transaction. Thus, an SCP byte access is in essence a 16–bit operation. Note that this 16–bit
operation can take place by means of two 8–bit accesses or a single 16–bit access.
SCP TRANSACTIONS
There are six types of SCP transactions.
1. SCP Nibble Register Read
2. SCP Nibble Register Write
3. SCP Byte Register Read
4. SCP Byte Register Write
5. SCP Merged Read
6. SCP Merged Write
The following sections contain a discussion on each type of SCP transaction.
SCP Nibble Register Read
A nibble register read is an 8–bit SCP transaction. Figure 5–1 illustrates this process. To initiate an
SCP nibble register read, the SCPEN pin is brought low. Following this, a read/write (R/W) bit, followed
by three primary address bits (A0 – A2 = 0 to 6), are shifted (MSB first) into an intermediate buffer
register on the first four rising edges of SCPCLK, following the high–to–low transition of SCPEN. If
a read operation is to be performed, then R/W should be a 1. The three address bits clocked in after
the R/W bit select which nibble register is to be read. The contents of this nibble register are shifted
out on SCP Tx on the subsequent four falling edges of SCPCLK; i.e., the four falling edges of SCPCLK
after the rising edge of SCPCLK, which clocked in the last address bit (LSB). SCPEN should be brought
MC145574
SERIAL CONTROL PORT
5
5–1