LH79525N0Q100A1 NXP Semiconductors, LH79525N0Q100A1 Datasheet - Page 5

• Manufacturer Part Number: LH79525N0Q100A1
• Description: Microcontrollers (MCU) LCD USB ETH'NET MMU
• Manufacturer: NXP Semiconductors

Specifications of LH79525N0Q100A1

• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 16 KB
• Interface Type: I2C, I2S, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 76.205 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / Rohs Status: Details
• Other names: LH79525N0Q100A1;55

System-on-Chip
SIGNAL DESCRIPTIONS
Preliminary data sheet
LFBGA
M15
M14
M13
M16
R11
P10
R10
N16
N15
P16
N14
G15
D13
E13
E14
G14
G16
H14
H15
H16
K16
K15
PIN
T12
T11
T10
L13
F14
L16
L15
L14
J15
J14
R9
R8
R7
P9
T9
T8
P8
T7
P7
T6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
SDCLK
SDCKE
DQM0
DQM1
DQM2
DQM3
nDCS0
nDCS1
nRAS
nCAS
nCS0/PM0
nCS1/PM1
nCS2/PM2
nCS3/PM3
nBLE0/PM4
nBLE1/PM5
nBLE2/PM6
nBLE3/PM7
SIGNAL NAME
TYPE
I/O
O
O
O
O
O
O
O
O
O
O
Table 2. LH79524 Pin Descriptions
External Address Bus
External Data Bus
SDRAM Clock
SDRAM Clock Enable
Data Mask Output to SDRAMs
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
Static Memory Chip Select; multiplexed with GPIO Port M[3:0] (output only)
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[7:4] (output only)
NXP Semiconductors
Rev. 01 — 16 July 2007
DESCRIPTION
LH79524/LH79525
5