LH7A404N0F092B3 NXP Semiconductors, LH7A404N0F092B3 Datasheet - Page 36

• Manufacturer Part Number: LH7A404N0F092B3
• Description: Microcontrollers (MCU) LCD USB FS/HOST MMU LFBGA324
• Manufacturer: NXP Semiconductors

Specifications of LH7A404N0F092B3

• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 80 KB
• Interface Type: AC97, EBI, IrDA, Microwire, SPI, SSI, SSP, UART, USB
• Maximum Clock Frequency: 266 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / Rohs Status: Details
• Other names: LH7A404N0F092B3;55

LH7A404
36
A[27:0]
D[31:0]
nCS[7:0]
nWE
nOE
nBLE (Write)
nBLE (Read)
SA[13:0]
A[17:16]/
SB[1:0]
D[31:0]
nCAS
nRAS
nSWE
SCKE[1:0]
DQM[3:0]
nSCS[3:0]
nPCREG
SIGNAL
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE
Input
Input
—
LOAD
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period])
—
—
—
SYNCHRONOUS MEMORY INTERFACE SIGNALS (‘-092’ parts
tOVDREG
tOHDREG
SYMBOL
tCSHWE
tOVSDW
tOHSDW
tCSHBE
tDVWE
tDHWE
tAVWE
tOVDQ
tDHCS
tDSOE
tDHOE
tAHOE
tOVCA
tOHCA
tOVRA
tOHRA
tOVSC
tOHSC
tDVBE
tDHBE
tDSCS
tDSBE
tDHBE
tAVCS
tAHCS
tAVOE
tAVBE
tAVBE
tAHBE
tOVC0
PCMCIA INTERFACE SIGNALS (+ [wait states × HCLK period])
tBEW
tOHD
tBER
tOVA
tOHA
tOVB
tOVD
tIHD
tWC
tWS
tWE
tISD
tRC
tOE
tCS
Table 12. AC Signal Characteristics
4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Read Cycle Time
4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Write Cycle Time
2 × tHCLK – 3.0 ns 2 × tHCLK + 3.0 ns nCSx Width
2 × tHCLK – 3.0 ns 2 × tHCLK + 3.0 ns nOE Width
2 × tHCLK – 5.0 ns 2 × tHCLK + 3.0 ns nBLE Width
4 × tHCLK – 5 ns
tHCLK – 6.0 ns
tHCLK – 7.0 ns
tHCLK – 5.0 ns
tHCLK – 7.0 ns
tHCLK – 4.0 ns
tHCLK – 2.0 ns
tHCLK – 4.0 ns
tHCLK – 1.0 ns
tHCLK – 4.0 ns
tHCLK – 5.0 ns
tHCLK – 2.0 ns
tHCLK – 2.0 ns
1.5/2.5 ns
tHCLK ns
1.5/1.5 ns
1.0/1.5 ns
1.5/2 ns
1.5/2 ns
1.5/2 ns
1.5/2 ns
tHCLK
tHCLK
tHCLK
tHCLK
15 ns
15 ns
15 ns
1.5ns
MIN.
0 ns
0 ns
0 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
NXP Semiconductors
—
—
—
tHCLK + 2.0 ns
tHCLK + 3.0 ns
tHCLK + 4.5 ns
tHCLK + 1.0 ns
tHCLK + 2.0 ns
tHCLK + 4.5 ns
tHCLK + 3.0 ns
tHCLK + 4.5 ns
tHCLK – 2.0 ns
tHCLK – 1.0 ns
tHCLK + 5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
5.5/7.5 ns
tHCLK ns
tHCLK ns
tHCLK
tHCLK
tHCLK
tHCLK
tHCLK
MAX.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Wait State Width
Data Valid to Write Edge (nWE invalid)
Data Hold after Write Edge (nWE invalid)
Data Valid to nBLE Invalid
Data Hold after nBLE Invalid
Data Setup to nCSx Invalid
Data Hold to nCSx Invalid
Data Setup to nOE Invalid
Data Hold to nOE Invalid
Data Setup to nBLE Invalid
Data Hold to nBLE Invalid
Address Valid to nCSx Valid
Address Hold after nCSx Invalid
nWE Width
Address Valid to nWE Valid
nCSx Hold after nWE Invalid
Address Valid to nOE Valid
Address Hold after nOE Invalid
nBLE Width
Address Valid to nBLE Valid
nCSx Hold after nBLE Invalid
Address Valid to nBLE Valid
Address Hold after nBLE Invalid
Address Valid
Address Hold
Bank Select Valid
Data Hold
Data Valid
Data Setup
Data Hold
CAS Valid
CAS Hold
RAS Valid
RAS Hold
Write Enable Valid
Write Enable Hold
Clock Enable Valid
Data Mask Valid
Synchronous Chip Select Valid
Synchronous Chip Select Hold
nREG Valid
nREG Hold
/
’-000’ parts)
DESCRIPTION
32-Bit System-on-Chip
Preliminary data sheet
NOTES
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