ADV7321KSTZ Analog Devices Inc, ADV7321KSTZ Datasheet
ADV7321KSTZ
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ADV7321KSTZ Summary of contents
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FEATURES High definition (HD) input formats 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb Fully compliant with SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i) RGB in 3-bit × 10-bit 4:4:4 input format HDTV RGB supported RGB, ...
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ADV7320/ADV7321 TABLE OF CONTENTS Features .............................................................................................. 1 General Features ............................................................................... 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 Terminology ...................................................................................... 5 Specifications..................................................................................... 6 Dynamic Specifications ............................................................... 7 Timing ...
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CGMS Functionality...................................................................65 Appendix 2—SD Wide Screen Signaling .....................................68 Appendix 3—SD Closed Captioning............................................69 Appendix 4—Test Patterns.............................................................70 Appendix 5—SD Timing Modes...................................................73 Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = ............................73 Mode 0 (CCIR-656)—Master ...
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ADV7320/ADV7321 DETAILED FEATURES HD programmable features (720p/1080i/1035i) 2× oversampling (148.5 MHz) Internal test pattern generator Color hatch, black bar, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS-A (720p/1080i) ED ...
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HD PIXEL Y INPUT DE- TEST INTER- CR PATTERN LEAVE CLKIN_B CB P_HSYNC TIMING P_VSYNC GENERATOR P_BLANK S_HSYNC TIMING S_VSYNC GENERATOR S_BLANK CLKIN_A CB DE- TEST INTER- CR PATTERN LEAVE SD PIXEL Y INPUT TERMINOLOGY SD: standard definition video, conforming ...
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ADV7320/ADV7321 SPECIFICATIONS V = 2.375 V to 2.625 2.375 V to 2.625 specifications (0°C to 70°C), unless otherwise noted. MIN MAX Table 2. Parameter Min STATIC PERFORMANCE 1 Resolution Integral ...
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DYNAMIC SPECIFICATIONS V = 2.375 V to 2.625 2.375 V to 2.625 specifications (0°C to 70°C), unless otherwise noted. MIN MAX Table 3. Parameter PS MODE Luma Bandwidth Chroma Bandwidth ...
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ADV7320/ADV7321 TIMING SPECIFICATIONS V = 2.375 V to 2.625 2.375 V to 2.625 specifications (0°C to 70°C), unless otherwise noted. MIN MAX Table 4. Parameter 1 MPU PORT SCLOCK Frequency ...
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TIMING DIAGRAMS CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME OUTPUT ...
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ADV7320/ADV7321 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 S9–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME OUTPUT ...
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CLKIN_A P_VSYNC, CONTROL P_HSYNC, INPUTS P_BLANK Cb0 Y0 Y9– CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA ...
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ADV7320/ADV7321 CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 Cb0 CLKIN_A S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD ...
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CLKIN_B t 9 P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Cb0 CLKIN_A S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 t = CLOCK HIGH TIME CLOCK LOW TIME 10 t ...
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ADV7320/ADV7321 CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0/Y9–Y0* Y0 C9–C0 Cb0 CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21 CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP ...
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P_HSYNC P_VSYNC a P_BLANK Y9– CLKCYCLES FOR 525p CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p Figure 16. PS 4:2:2 10-Bit Interleaved Input ...
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ADV7320/ADV7321 ABSOLUTE MAXIMUM RATINGS Table 5. 1 Parameter V to AGND DGND GND_IO DD_IO Digital Input Voltage to DGND AGND to DGND DGND to GND_IO AGND to GND_IO Ambient ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD_IO V DGND Table 6. Pin Function Descriptions Pin No. Mnemonic Input/Output 11, 57 DGND G 40 AGND G 32 CLKIN_A I 63 CLKIN_B I 45, 36 COMP1, O COMP2 44 DAC A O ...
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ADV7320/ADV7321 Pin No. Mnemonic Input/Output RESET I 47 SET1 SET2 22 SCLK I 21 SDA I/O 20 ALSB DD_IO 10, ...
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TYPICAL PERFORMANCE CHARACTERISTICS PS Pr/Pb RESPONSE. LINEAR INTERPOLATION (4:2:2 TO 4:4:4) 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 20. PS—UV 8× Oversampling Filter (Linear) PS Pr/Pb RESPONSE. SSAF ...
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ADV7320/ADV7321 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 26. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 27. Luma PAL Low-Pass ...
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FREQUENCY (MHz) Figure 32. Luma SSAF Filter—Programmable Responses – FREQUENCY (MHz) Figure 33. ...
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ADV7320/ADV7321 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 38. Chroma 2.0 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. Chroma 1.3 ...
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MPU PORT DESCRIPTION The ADV7320/ADV7321 support a 2-wire serial (I compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the ...
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ADV7320/ADV7321 SDATA SCLOCK WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER S 9 1–7 9 ...
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REGISTER ACCESS The MPU can write to or read from all registers of the ADV7320/ADV7321 except the subaddress registers, which are write only registers. The subaddress register selected determines which register the next read or write operation will access. All ...
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ADV7320/ADV7321 Table 8. Registers 0x02 to 0x0F SR7– SR0 Register Bit Description 0x02 Mode Register 0 Reserved Test Pattern Black Bar Manual RGB Matrix Adjust Sync on RGB 1 RGB/YPrPb Output SD Sync HD Sync 0x03 RGB Matrix 0 0x04 ...
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Table 9. Registers 0x10 to 0x11 SR7– SR0 Register Bit Description 0x10 HD Mode HD Output Standard Register 1 Input Sync Format HD/ED Input Mode 0x11 HD Mode HD Pixel Data Valid Register 2 HD Test Pattern Enable HD Test ...
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ADV7320/ADV7321 Table 10. Register 0x12 SR7– SR0 Register Bit Description 0x12 HD Mode HD Y Delay with Register 3 Respect to Falling Edge of HSYNC HD Color Delay with Respect to Falling Edge of HSYNC HD CGMS HD CGMS CRC ...
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Table 12. Register 0x15 SR7– SR0 Register Bit Description 0x15 HD Mode Reserved Register 6 HD RGB Input HD Sync on PrPb HD Color DAC Swap HD Gamma Curve A HD Gamma Curve B HD Gamma Curve Enable HD Adaptive ...
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ADV7320/ADV7321 Table 13. Registers 0x16 to 0x37 SR7– SR0 Register Bit Description 1 0x16 HD Y Level 0x17 Level 1 0x18 HD Cb Level 0x19 Reserved 0x1A Reserved 0x1B Reserved 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F ...
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Table 14. Registers 0x38 to 0x3D SR7– SR0 Register Bit Description 0x38 HD Adaptive Filter HD Adaptive Filter Gain 1 Gain 1, Value A HD Adaptive Filter Gain 1, Value B 0x39 HD Adaptive Filter HD Adaptive Filter Gain 2 ...
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ADV7320/ADV7321 Table 15. Registers 0x3E to 0x43 SR7– SR0 Register Bit Description 0x3E Reserved 0x3F Reserved 0x40 SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 0x41 Reserved 0x42 SD Mode Register 1 SD PrPb SSAF SD ...
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Table 16. Registers 0x44 to 0x49 SR7– SR0 Register Bit Description 0x44 SD Mode SD VSYNC -3H Register 3 SD RTC/TR/SCR SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap 0x45 Reserved 0x46 SD Mode ...
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ADV7320/ADV7321 Table 17. Registers 0x4A to 0x58 SR7– SR0 Register Bit Description 0x4A SD Timing SD Slave/Master Mode Register 0 SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset 0x4B SD Timing SD ...
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Table 18. Registers 0x59 to 0x64 SR7– SR0 Register Bit Description 0x59 SD CGMS/WSS 0 SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS 0x5A SD CGMS/WSS 1 SD CGMS/WSS Data ...
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ADV7320/ADV7321 Table 19. Registers 0x65 to 0x7C SR7– SR0 Register Bit Description 0x65 SD DNR 2 DNR Input Select DNR Mode DNR Block Offset 0x66 SD Gamma A SD Gamma Curve A Data Points 0x67 SD Gamma A SD Gamma ...
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Table 20. Registers 0x7D to 0x91 SR7- SR0 Register 1 Bit Description 0x7D Reserved 0x7E Reserved 0x7F Reserved 0x80 Macrovision MV Control Bits 0x81 Macrovision MV Control Bits 0x82 Macrovision MV Control Bits 0x83 Macrovision MV Control Bits 0x84 Macrovision ...
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ADV7320/ADV7321 INPUT CONFIGURATION When 10-bit input data is applied, the following bits must be set to 1: Address 0x13, Bit 2 (HD 10-bit enable) Address 0x48, Bit 4 (SD 10-bit enable) Note that the ADV7320 defaults to simultaneous SD and ...
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The 8- or 10-bit SD data must be compliant with ITU-R BT.601/656 in 4:2:2 format. SD data is input on Pins S9 to S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pins S9 ...
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ADV7320/ADV7321 Table 22. Input Configurations Input Format Total Bits ITU-R BT.656 (See Table 21 Only 8 (27 MHz clock) 10 (27 MHz clock) 8 (54 MHz clock) 10 (54 MHz clock ...
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FEATURES OUTPUT CONFIGURATION Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly. Table 23. Output Configuration in SD Only Mode RGB/YUV Output SD DAC Output 1 ...
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ADV7320/ADV7321 HD ASYNC TIMING MODE [Subaddress 0x10, Bits 3 and 2] For any input data that does not conform to the standards selectable in input mode (Subaddress 0x10) asynchronous timing mode can be used to interface to the ADV7320/ADV7321. Timing ...
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HD TIMING RESET A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 0x14, Bit 0] from this state, the horizontal and vertical counters remain reset. When this bit is set back ...
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ADV7320/ADV7321 DISPLAY 307 NO F RESET APPLIED SC DISPLAY 307 F RESET APPLIED SC COMPOSITE ADV7183A 1 VIDEO DECODER H/L TRANSITION COUNT START LOW 128 RTC TIME SLOT 01 NOTES 1 FOR EXAMPLE, VCR OR CABLE PLL INCREMENT ...
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RESET SEQUENCE A reset is activated with a high-to-low transition on the RESET pin (Pin 33) according to the timing specifications, and the ADV7320/ADV7321 revert to the default output configuration. Figure 63 illustrates the RESET timing sequence. SD VCR FF/RW ...
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ADV7320/ADV7321 VERTICAL BLANKING INTERVAL The ADV7320/ADV7321 accepts input data that contains VBI data (such as CGMS, WSS, VITS and HD modes. For the SMPTE 293M (525p) standard, VBI data can be inserted on Lines ...
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SQUARE PIXEL TIMING MODE [Address 0x42, Bit 4] In square pixel mode, the following timing diagrams apply. ANALOG VIDEO INPUT PIXELS Y NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE VIDEO LINE HSYNC FIELD PAL = ...
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ADV7320/ADV7321 FILTERS Table 27 shows an overview of the programmable filters available on the ADV7320/ADV7321. Table 27. Selectable Filters Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD ...
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PS/HD Sinc Filter [Subaddress 0x13, Bit 3] 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (MHz) Figure 67. HD Sinc Filter Enabled 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 ...
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ADV7320/ADV7321 This is reflected in the preprogrammed values for GY = 0x13B 0x3B 0x93 0x248, and RV = 0x1F0. If the RGB matrix is enabled and another input standard (such PS) ...
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SD Hue Adjust Value [Subaddress 0x60] The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, that is, the ...
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ADV7320/ADV7321 SD Brightness Detect [Subaddress 0x7A] The ADV7320/ADV7321 allow monitoring the brightness level of the incoming video data. Brightness detect is a read-only register. Double Buffering [Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2] Double-buffered registers are updated once per ...
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PROGRAMMABLE DAC GAIN CONTROL DACs A, B, and C are controlled by Register 0A. DACs D, E, and F are controlled by Register 0B. 2 The I C control registers will adjust the output signal gain up or down from ...
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ADV7320/ADV7321 For lengths 240 points, the gamma correction curve is calculated as follows γ where gamma corrected output linear input signal. γ = gamma power factor. To program the gamma ...
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HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS [Subaddresses 0x20, 0x38 to 0x3D] There are three filter modes available on the ADV7320/ADV7321: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal ...
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ADV7320/ADV7321 HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings listed in Table 34 were used to achieve ...
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Adaptive Filter Control Application Figure 75 and Figure 76 show how a typical signal is processed by the adaptive filter control block in Mode A. Figure 75. Input Signal to Adaptive Filter Control Figure 76. Output Signal with Adaptive Filter ...
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ADV7320/ADV7321 DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER NOISE SIGNAL PATH INPUT FILTER BLOCK FILTER OUTPUT Y DATA < THRESHOLD? INPUT FILTER OUTPUT > THRESHOLD MAIN SIGNAL PATH DNR ...
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FILTER D 0.8 FILTER C 0.6 0.4 FILTER B 0.2 FILTER FREQUENCY (Hz) Figure 81. DNR Input Select DNR MODE CONTROL [Address 0x65, Bit 4] This bit is used to select the ...
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ADV7320/ADV7321 VOLTS IRE:FLT 0 VOLTS IRE:FLT 0.5 0 –2 100 L135 – Figure 83. Address 0x42, Bit 100 L135 – Figure ...
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HSYNC/VSYNC OUTPUT CONTROL The ADV7320/ADV7321 have the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on P_HSYNC / P_VSYNC , outputting the respective signals on the S_HSYNC and S_VSYNC pins. 1 ...
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ADV7320/ADV7321 BOARD DESIGN AND LAYOUT DAC TERMINATION AND LAYOUT CONSIDERATIONS The ADV7320/ADV7321 contain an on-board voltage reference. The ADV7320/ADV7321 can be used with an external V (AD1580). REF The R resistors are connected between the R SET and are used ...
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CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 GROUP DELAY (Seconds) –40 –50 –60 –70 –80 –90 1M 10M 100M FREQUENCY (Hz) Figure 89. Filter Plot for Output Filter for PS, 8× Oversampling CIRCUIT FREQUENCY RESPONSE 0 MAGNITUDE (dB) –10 –20 ...
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ADV7320/ADV7321 Analog Signal Interconnect Locate the ADV7320/ADV7321 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. For optimum performance, each analog output should be source- and load-terminated, as shown in Figure ...
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APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM PS CGMS Data Registers [Subaddresses 0x21, 0x22, 0x23] 525p Using the vertical blanking interval 525p system, 525p CGMS conforms to the CGMS-A EIA-J CPR1204-1 (March 1998) transfer method of video identification information ...
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ADV7320/ADV7321 +700mV 70% ± 10% 0mV –300mV 5.8 μ s ± 0.15 μ PEAK WHITE 500mV ± 25mV SYNC LEVEL 5.5μs ± 0.125μs +100 IRE +70 IRE 0 IRE –40 IRE 11.2μs REF ...
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REF 70% ± 10% 0mV –300mV 4T 3.128 μ s ± 90ns +700mV REF 70% ± 10% 0mV –300mV 4T 4.15μs ± 60ns C10 C11 C12 C13 C14 C15 ...
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ADV7320/ADV7321 APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddresses 0x59, 0x5A, 0x5B] The ADV7320/ADV7321 support wide screen signaling (WSS) conforming to the ETS 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device ...
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APPENDIX 3—SD CLOSED CAPTIONING [Subaddresses 0x51 to 0x54] The ADV7320/ADV7321 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields ...
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ADV7320/ADV7321 APPENDIX 4—TEST PATTERNS The ADV7320/ADV7321 can generate SD and HD test patterns CH2 200mV M 10.0μs T 30.6000μs Figure 99. NTSC Color Bars T 2 CH2 200mV M 10.0μs 30.6000μs T Figure 100. PAL Color Bars T ...
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T 2 CH2 200mV M 4.0μs CH2 T 1.82872ms Figure 105. 525p Field Pattern T 2 CH2 200mV M 4.0μs CH2 1.84176ms T Figure 106. 625p Field Pattern T 2 EVEN (−35 mV, 0 mV, 7 mV, 14 mV, 21 ...
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ADV7320/ADV7321 The register settings in Table 41 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed ...
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APPENDIX 5—SD TIMING MODES [Subaddress 0x4A] MODE 0 (CCIR-656)—SLAVE OPTION (TIMING REGISTER 0 TR0 = The ADV7320/ADV7321 are controlled by the SAV (start active video) and EAV (end active video) time codes ...
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ADV7320/ADV7321 MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = The ADV7320/ADV7321 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes ...
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DISPLAY 622 623 624 625 ODD FIELD EVEN FIELD F DISPLAY 309 310 311 312 313 H V ODD FIELD EVEN FIELD F ANALOG VIDEO VERTICAL BLANK VERTICAL ...
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ADV7320/ADV7321 MODE 1—SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates ...
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MODE 1—MASTER OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates ...
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ADV7320/ADV7321 MODE 2— SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates ...
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MODE 2—MASTER OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the ...
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ADV7320/ADV7321 MODE 3—MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 accept or generate hori- zontal sync and odd/even field ...
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APPENDIX 6—HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 122. 1080i HSYNC and ...
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ADV7320/ADV7321 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 123. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 ...
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RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars 700mV 300mV 700mV 300mV 700mV 300mV Figure 127. PS RGB Output Levels 700mV 525mV 300mV 0mV 700mV 300mV 0mV 700mV 300mV 0mV Figure 128. PS RGB Output Levels—RGB Sync Enabled 525mV 525mV 525mV ...
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ADV7320/ADV7321 YPrPb LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV Figure 131. Pb Levels—NTSC 700mV Figure 132. Pb Levels—PAL 700mV Figure 133. Pr Levels—NTSC 700mV Figure 134. Pr Levels—PAL 700mV 300mV Figure 135. Y Levels—NTSC 700mV 300mV Figure 136. Y Levels—PAL ...
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VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72 μ s FRAMES SELECTED 1, ...
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ADV7320/ADV7321 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE F 0 INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 ...
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ACTIVE VIDEO 522 523 524 525 Figure 145. SMPTE 293M (525p) ACTIVE VIDEO 1 2 622 623 624 625 4 Figure 146. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 747 748 749 750 Figure 147. ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADV7320KSTZ 0°C to 70°C 1 ADV7321KSTZ 0°C to 70°C EVAL-ADV7320EB EVAL-ADV7321EB Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05067–0–5/06(A) ...