STA015B$ STMicroelectronics, STA015B$ Datasheet - Page 22

• Manufacturer Part Number: STA015B$
• Description: DECODER AUDIO MPEG 2.5 8X8LFBGA
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA015B$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -

STA015
CMD_INTERRUPT
Address: 0x16 (22)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care;
0 = normal operation;
1 = write into I
The INTERRUPT is used to give STA015 the command to write into the I
ters: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register,
setting it to a non-zero value.
DATA_REQ_ENABLE
Address: 0x18 (24)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data
request signal, used for multimedia mode.
The buffered Output Clock has the same frequency than the input clock (XTI)
SYNCSTATUS
Address: 0x40 (64)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
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MSB
MSB
b7
b7
X
X
X
MSB
b7
X
b6
b6
X
X
X
2
C/Ancillary Data
b6
X
b5
b5
X
X
X
b5
X
b4
b4
X
X
X
b3
b3
X
X
X
b4
X
b2
b2
X
0
1
b3
X
SS1
b1
b1
X
X
0
0
1
b2
LSB
LSB
SS0
X
b0
b0
X
X
0
1
0
2
C/Ancillary Data Buffer (Regis-
Research of sync word
Wait for Confirmation
buffered output clock
b1
X
request signal
Synchronised
Description
Description
LSB
b0
0
1