STA015B$ STMicroelectronics, STA015B$ Datasheet - Page 33

• Manufacturer Part Number: STA015B$
• Description: DECODER AUDIO MPEG 2.5 8X8LFBGA
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA015B$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -

PCMCROSS
Address: 0x56 (86)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The default configuration for this register is ’0x00’.
MFSDF (X)
Address: 0x61 (97)
Type: R/W
Software Reset: 0x07
Hardware Reset: 0x07
The register contains the values for PLL X divider (see Fig. 7).
The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incom-
ing bitstream. This value can be even set by the user to select the PCM interface configuration.
The VCO output frequency is divided by (X+1). This register is a reference for 32KHz and 48KHz input
bitstream.
DAC_CLK_MODE (99)
Address: 0x63
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
This register is used to select the operating mode for OCLK clock signal. If it is set to “1”, the OCLK fre-
quency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the
incoming bitstream changes. It the MODE flag is set to f0f, the OCLK frequency changes, and can be set
to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected,
MSB
b7
X
X
X
X
MSB
MSB
b7
b7
X
X
b6
X
X
X
X
b5
X
X
X
X
b6
b6
X
X
b4
X
X
X
X
b3
X
X
X
X
b5
b5
X
X
b2
X
X
X
X
M4
b1
b4
b4
X
0
0
1
1
LSB
b0
0
1
0
1
Left channel is mapped on the left output.
Right channel is mapped on the Right output
Left channel is duplicated on both Output channels.
Right channel is duplicated on both Output channels
Right and Left channels are toggled
M3
b3
b3
X
M2
b2
b2
X
Description
M1
b1
b1
X
MODE
STA015
LSB
LSB
M0
b0
b0
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