PCA9500BS,118 NXP Semiconductors, PCA9500BS,118 Datasheet - Page 11

• Manufacturer Part Number: PCA9500BS,118
• Description: IC I/O EXPANDER I2C 8B 16HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9500BS,118

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Includes: EEPROM, POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3351-2; 935273812118; PCA9500BS-T

NXP Semiconductors
PCA9500_4
Product data sheet
8.2 System configuration
8.3 Acknowledge
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 17. System configuration
Fig 18. Acknowledgement on the I
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
SCL from master
by transmitter
data output
by receiver
data output
Rev. 04 — 15 April 2009
condition
START
RECEIVER
SLAVE
S
Figure
8-bit I
2
C-bus
1
2
17).
C-bus and SMBus I/O port with 2-kbit EEPROM
TRANSMITTER/
RECEIVER
SLAVE
2
acknowledgement
not acknowledge
TRANSMITTER
clock pulse for
acknowledge
MASTER
8
PCA9500
© NXP B.V. 2009. All rights reserved.
002aaa987
9
TRANSMITTER/
RECEIVER
MASTER
002aaa381
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