PCA9557PW,112 NXP Semiconductors, PCA9557PW,112 Datasheet - Page 10

• Manufacturer Part Number: PCA9557PW,112
• Description: IC I/O EXPANDER I2C 8B 16TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9557PW,112

• Package / Case: 16-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Current: 50 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5028; 935270669112; PCA9557PW; PCA9557PW,112; PCA9557PW

NXP Semiconductors
PCA9557
Product data sheet
Fig 12. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
8.2 System configuration
8.3 Acknowledge
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 11. Definition of START and STOP conditions
SDA
SCL
RECEIVER
SLAVE
START condition
S
TRANSMITTER/
Rev. 06 — 11 June 2008
RECEIVER
SLAVE
Figure
TRANSMITTER
12).
MASTER
8-bit I
2
C-bus and SMBus I/O port with reset
TRANSMITTER/
RECEIVER
MASTER
SLAVE
STOP condition
P
MULTIPLEXER
PCA9557
© NXP B.V. 2008. All rights reserved.
I
2
C-BUS
002aaa966
mba608
SDA
SCL
10 of 26