PCF8574AT/3,512 NXP Semiconductors, PCF8574AT/3,512 Datasheet - Page 8

• Manufacturer Part Number: PCF8574AT/3,512
• Description: IC I/O EXPANDER I2C 8B 16SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCF8574AT/3,512

• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Interface: I²C
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 100KHz
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCF
• Number Of Lines (input / Output): 9
• Operating Supply Voltage: 2.5 V to 6 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Clock Frequency: 100 KHz
• Mounting Style: SMD/SMT
• Number Of Output Lines: 9
• Output Current: 25 mA
• Output Voltage: 2.4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3987-5; 935275581512; PCF8574ATD; PCF8574ATD

Philips Semiconductors
6.4
The number of data bytes transferred between the start
and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.8). The acknowledge bit is a
HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
2002 Nov 22
handbook, full pagewidth
Remote 8-bit I/O expander for I
Acknowledge
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
condition
START
S
Fig.8 Acknowledgment on the I
2
C-bus
1
8
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a stop condition.
2
2
C-bus.
not acknowledge
acknowledge
8
acknowledgement
clock pulse for
9
MBC602
Product specification
PCF8574