PCA9500PW,112 NXP Semiconductors, PCA9500PW,112 Datasheet - Page 4

IC I/O EXPANDER I2C 8B 16TSSOP

PCA9500PW,112

Manufacturer Part Number
PCA9500PW,112
Description
IC I/O EXPANDER I2C 8B 16TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9500PW,112

Package / Case
16-TSSOP
Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
No
Frequency - Clock
400kHz
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
EEPROM, POR
Logic Family
PCA9500
Number Of Lines (input / Output)
8.0 / 8.0
Operating Supply Voltage
2.5 V to 3.6 V
Power Dissipation
400 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I/O Expander
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
8.0
Number Of Output Lines
8.0
Output Current
25 mA
Output Voltage
5 V
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
TSSOP
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1025-5
935271534112
PCA9500PW
NXP Semiconductors
PCA9500_4
Product data sheet
6.2 Pin description
Table 3.
[1]
Symbol
A0
A1
A2
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V
WC
SCL
SDA
V
Fig 4.
SS
DD
HVQFN16 package supply ground is connected to both V
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias need to be incorporated in the
printed-circuit board in the thermal pad region.
Pin configuration for HVQFN16
Pin description
Pin
SO16, TSSOP16
1
2
3
4
5
6
7
9
10
11
12
8
13
14
15
16
Rev. 04 — 15 April 2009
index area
terminal 1
IO0
IO1
IO2
A2
8-bit I
HVQFN16
15
16
1
2
3
4
5
7
8
9
10
6
11
12
13
14
[1]
1
2
3
4
2
Transparent top view
C-bus and SMBus I/O port with 2-kbit EEPROM
PCA9500BS
Description
address lines (internal pull-up)
quasi-bidirectional I/O pins
supply ground
active LOW write control pin
I
I
supply voltage
2
2
C-bus serial clock
C-bus serial data
SS
pin and exposed center pad. V
12
11
10
9
002aae584
SCL
WC
IO7
IO6
PCA9500
© NXP B.V. 2009. All rights reserved.
SS
pin must be
4 of 26

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