PCA9555PW,112 NXP Semiconductors, PCA9555PW,112 Datasheet
PCA9555PW,112
Specifications of PCA9555PW,112
935269569112
PCA9555PW
PCA9555PW
Related parts for PCA9555PW,112
PCA9555PW,112 Summary of contents
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... The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I enhance the NXP Semiconductors family of I include higher drive capability I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9555 consists of two 8-bit Confi ...
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... NXP Semiconductors I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24 3. Ordering information Table 1. Type number Package PCA9555N PCA9555D PCA9555DB PCA9555PW TSSOP24 PCA9555BS PCA9555HF 3.1 Ordering options Table 2. Type number ...
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... NXP Semiconductors 4. Block diagram SCL SDA Fig 1. 5. Pinning information 5.1 Pinning IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 Fig 2. PCA9555_8 Product data sheet 16-bit I PCA9555 2 I C-BUS/SMBus INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at reset. Block diagram of PCA9555 ...
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... NXP Semiconductors INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 V SS Fig 4. terminal 1 index area IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 Fig 6. PCA9555_8 Product data sheet 16-bit SDA 3 22 SCL IO1_7 6 19 IO1_6 PCA9555DB 7 18 IO1_5 8 17 IO1_4 9 16 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Symbol INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 V SS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A0 SCL SDA V DD [1] HVQFN and HWQFN package die supply ground is connected to both the V pad. The V ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Fig 8. 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission used as a pointer to determine which of the following registers will be written or read. Table 4. Command PCA9555_8 ...
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... NXP Semiconductors 6.2.2 Registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. ...
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... NXP Semiconductors 6.2.5 Registers 6 and 7: Configuration registers This register configures the directions of the I/O pins bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output ...
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... NXP Semiconductors data from shift register data from shift register configuration write pulse read pulse data from shift register write polarity Fig 9. 6.5 Bus transactions 6.5.1 Writing to the port registers Data is transmitted to the PCA9555 by sending the device address and setting the least signifi ...
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SCL slave address SDA START condition R/W write to port data out from port 0 data out from port 1 Fig 10. Write ...
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... NXP Semiconductors 6.5.2 Reading the port registers In order to read data from the PCA9555, the bus master must first send the PCA9555 address with the least significant bit set to a logic 0 (see address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least signifi ...
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INT INT t t v(INT_N) rst(INT_N) SCL R/W slave address I0.x SDA ...
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DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT_N) rst(INT_N) SCL R/W slave address I0.x SDA ...
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... NXP Semiconductors 6.5.3 Interrupt output The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read (see output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around ...
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... NXP Semiconductors 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL ...
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... NXP Semiconductors 8. Application design-in information MASTER CONTROLLER SCL SDA INT GND Device address configured as 0100 000xb for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs. Fig 19. Typical application ...
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... NXP Semiconductors 9. Limiting values Table 13. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I tot T stg T amb PCA9555_8 Product data sheet 16-bit I Limiting values Parameter supply voltage voltage on an input/output pin output current input current supply current ground supply current ...
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... NXP Semiconductors 10. Static characteristics Table 14. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
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... NXP Semiconductors [2] Each I/O must be externally limited to a maximum and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. [3] The total current sourced by all I/Os must be limited to 160 mA. 6 (V) 5.0 4.0 (1) 3.0 (2) 2 ...
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... NXP Semiconductors 11. Dynamic characteristics Table 15. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 23. Definition of timing on the I 12. Test information Fig 24. Test circuitry for switching times Fig 25. Load circuit PCA9555_8 Product data sheet 16-bit HD;DAT HIGH SU;DAT 2 C-bus V I PULSE GENERATOR R = load resistor load capacitance includes jig and probe capacitance. ...
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... NXP Semiconductors 13. Package outline DIP24: plastic dual in-line package; 24 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 5.1 0.51 4 inches 0.2 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 28. Package outline SOT340-1 (SSOP24) ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Soldering of through-hole mount packages 16.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. ...
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... NXP Semiconductors 16.4 Package related soldering information Table 18. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. ...
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... NXP Semiconductors 18. Revision history Table 20. Revision history Document ID Release date PCA9555_8 20091022 • Modifications: Table 2 “Ordering “PCA9555PW” to “PCA9555” • Figure 13 “Read Input port register, scenario 1” • Figure 14 “Read Input port register, scenario 2” • Table 14 “Static • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Registers 6.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.2 Registers 0 and 1: Input port registers . . . . . . . 7 6 ...