PCA9535PW,118 NXP Semiconductors, PCA9535PW,118 Datasheet - Page 11
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PCA9535PW,118
Manufacturer Part Number
PCA9535PW,118
Description
IC I/O EXPANDER I2C 16B 24TSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9535BS118.pdf
(31 pages)
Specifications of PCA9535PW,118
Package / Case
24-TSSOP
Interface
I²C, SMBus
Number Of I /o
16
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9535
Number Of Lines (input / Output)
16.0 / 16.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
200 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I2C, SMBus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
16.0
Number Of Output Lines
16.0
Output Current
50 mA
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935273946118
PCA9535PW-T
PCA9535PW-T
PCA9535PW-T
PCA9535PW-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9535PW,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
PCA9535_PCA9535C_5
Product data sheet
Fig 10. Read from register
SDA
(cont.)
Remark: Transfer can be stopped at any time by a STOP condition.
S
START condition
S
(repeated)
START condition
6.5.2 Reading the port registers
0
0
1
slave address
1
0
slave address
0
In order to read data from the PCA9535/PCA9535C, the bus master must first send the
PCA9535/PCA9535C address with the least significant bit set to a logic 0 (see
“PCA9535; PCA9535C device
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9535/PCA9535C (see
Figure
the acknowledge clock pulse. After the first byte is read, additional bytes may be read but
the data will now reflect the information in the other register in the pair. For example, if you
read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the
bus master must not acknowledge the data.
0 A2 A1 A0
0 A2 A1 A0 1
acknowledge
10,
from slave
acknowledge
R/W
Figure 11
from slave
0
R/W
A
A
MSB
Rev. 05 — 15 September 2008
and
COMMAND BYTE
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
upper byte of register
data from lower or
DATA (first byte)
Figure
16-bit I
address”). The command byte is sent after the address and
12). Data is clocked into the register on the falling edge of
acknowledge
2
C-bus and SMBus, low power I/O port with interrupt
from slave
LSB
A
A
acknowledge
from master
PCA9535; PCA9535C
(cont.)
MSB
lower byte of register
data from upper or
DATA (last byte)
no acknowledge
from master
LSB
© NXP B.V. 2008. All rights reserved.
NA
002aac222
P
STOP
condition
Figure 6
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