PCA9506DGG,512 NXP Semiconductors, PCA9506DGG,512 Datasheet - Page 10
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PCA9506DGG,512
Manufacturer Part Number
PCA9506DGG,512
Description
IC I/O EXPANDER I2C 40B 56TSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9505DGG112.pdf
(34 pages)
Specifications of PCA9506DGG,512
Package / Case
56-TSSOP
Interface
I²C
Number Of I /o
40
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9506
Number Of Lines (input / Output)
40.0 / 40.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
500 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5.5 V
Logic Type
I/O Expander
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
40.0
Number Of Output Lines
40.0
Output Current
50 mA
Output Voltage
5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3354-5
935280798512
PCA9506DGG
935280798512
PCA9506DGG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9506DGG,512
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
Table 3.
Table 4.
Legend: * default value ‘X’ determined by the externally applied logic level.
PCA9505_9506
Product data sheet
Register #
(hex)
Mask Interrupt registers
20
21
22
23
24
25
26
27
Address
00h
01h
02h
03h
04h
Register summary
IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
D5
1
1
1
1
1
1
1
1
Register
IP0
IP1
IP2
IP3
IP4
7.3.1 IP0 to IP4 - Input Port registers
D4
0
0
0
0
0
0
0
0
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes
to these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The
polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to
logic 0.
D3
0
0
0
0
0
0
0
0
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
…continued
D2
0
0
0
0
1
1
1
1
All information provided in this document is subject to legal disclaimers.
D1
0
0
1
1
0
0
1
1
Symbol
I0[7:0]
I1[7:0]
I2[7:0]
I3[7:0]
I4[7:0]
D0
0
1
0
1
0
1
0
1
Rev. 4 — 3 August 2010
Symbol
MSK0
MSK1
MSK2
MSK3
MSK4
-
-
-
Access
R
R
R
R
R
40-bit I
Access
read/write
read/write
read/write
read/write
read/write
-
-
-
Value
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
2
C-bus I/O port with RESET, OE and INT
Description
Mask Interrupt register bank 0
Mask Interrupt register bank 1
Mask Interrupt register bank 2
Mask Interrupt register bank 3
Mask Interrupt register bank 4
reserved for future use
reserved for future use
reserved for future use
Input Port register bank 0
Input Port register bank 1
Input Port register bank 2
Input Port register bank 3
Input Port register bank 4
Description
PCA9505/06
© NXP B.V. 2010. All rights reserved.
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