PCA9535CD,112 NXP Semiconductors, PCA9535CD,112 Datasheet - Page 14

• Manufacturer Part Number: PCA9535CD,112
• Description: IC I/O EXPANDER I2C 16B 24SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9535CD,112

• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285271112; PCA9535CD; PCA9535CD

NXP Semiconductors
7. Characteristics of the I
PCA9535_PCA9535C_5
Product data sheet
6.5.3 Interrupt output
7.1.1 START and STOP conditions
7.1 Bit transfer
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read (see
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 13. Bit transfer
Fig 14. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 05 — 15 September 2008
14).
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
data valid
data line
stable;
Figure
PCA9535; PCA9535C
allowed
change
of data
13).
Figure
11). A pin configured as an
STOP condition
mba607
P
© NXP B.V. 2008. All rights reserved.
mba608
SDA
SCL
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