MT46H16M32LFCM-75 L TR Micron Technology Inc, MT46H16M32LFCM-75 L TR Datasheet - Page 82
![](/photos/31/34/313421/mfg557-90-vfbga_sml.jpg)
MT46H16M32LFCM-75 L TR
Manufacturer Part Number
MT46H16M32LFCM-75 L TR
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H16M32LFCM-75_L_TR.pdf
(98 pages)
Specifications of MT46H16M32LFCM-75 L TR
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
100mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
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Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Command
Address
DQS
DQS
DQS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DM
DM
DM
DQ
DQ
DQ
CK#
5, 6
5, 6
5, 6
CK
1
7
6
7
6
7
6
WRITE
Bank a,
Col b
T0
Notes:
2
t
t
t
DQSS
DQSS
DQSS
1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. D
D
IN
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
D
IN
T1
IN
b = data-in for column b.
D
IN
T1n
NOP
T2
T2n
82
T3
NOP
512Mb: x16, x32 Mobile LPDDR SDRAM
t
WR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3n
4
NOP
T4
Don’t Care
T4n
(a or all)
T5
PRE
Bank
© 2004 Micron Technology, Inc. All rights reserved.
3
WRITE Operation
Transitioning Data
T6
NOP
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