DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 54

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DS1878T+T&R

Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet

Specifications of DS1878T+T&R

Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SFP+ Controller with Digital LDD Interface
Table 01h, Register FBh: ALARM EN
54
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FBh
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
MEMORY TYPE
Layout is identical to ALARM
whether this memory exists in Table 01h or 05h.
BITS 5:4
BITS 2:0
LOS HI
BIT 7
BIT 7
BIT 6
BIT 3
LOS HI: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS HI alarm.
1 = Enables interrupt from LOS HI alarm.
LOS LO: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS LO alarm.
1 = Enables interrupt from LOS LO alarm.
RESERVED
BIAS MAX: Enables alarm to create internal signal FETG (see Figure 14) logic.
0 = Disables interrupt from BIAS MAX alarm.
1 = Enables interrupt from BIAS MAX alarm.
RESERVED
LOS LO
00h
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
PW2 or (PW1 and RWTBL1C)
Nonvolatile (SEE)
0
RESERVED
0
in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 89h) determines
RESERVED
BIAS MAX
RESERVED
RESERVED
RESERVED
BIT 0

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