DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 95

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 07h, Register 80h–A3h: DAC1 LUT
Table 07h, Register A4h–A7h: RESERVED
80h–A3h
SFP+ Controller with Digital LDD Interface
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
The DAC1 LUT is a set of registers assigned to hold the PWM profile for DAC1. The values in this table
determine the set point for DAC1. The temperature measurement is used to index the LUT (TINDEX, Table 02h,
Register 81h) in 4°C increments from -40°C to +100°C, starting at Register 80h. Register 80h defines the -40°C
to -36°C DAC1 value, Register 81h defines -36°C to -32°C DAC1 value, and so on. Values recalled from this
EEPROM memory table are written into the DAC1 VALUE (Table 02h, Registers 84h–85h) location, which holds
the value until the next temperature conversion. The part can be placed into a manual mode (DAC1 EN bit, Table
02h, Register 80h), where DAC1 can be directly controlled for calibration. If temperature compensation is not
required by the application, program the entire LUT to the desired DAC1 set point. The DAC1TC bit determines
whether the 8-bit LUT values are loaded into the upper 8 bits or lower 8 bits of the 9-bit DAC1. See the Delta-
Sigma Outputs (DAC1 and DAC2) section for more information.
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
These registers are reserved.
BIT 7
______________________________________________________________________________________
2
7
2
6
00h
PW2 or (PW1 and RWTBL78) and (PW1 and RTBL78)
PW2 or (PW1 and RWTBL78)
Nonvolatile (EE)
00h
PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)
PW2 or (PW1 and RWTBL78)
Nonvolatile (EE)
2
5
2
4
2
3
Table 07h Register Descriptions
2
2
2
1
BIT 0
2
0
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