AD9844AJSTRL Analog Devices Inc, AD9844AJSTRL Datasheet - Page 10

• Manufacturer Part Number: AD9844AJSTRL
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9844AJSTRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9844A
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Register
Name
Operation
VGA Gain
Clamp Level
Control
CDS Gain
Internal use only, must be set to zero.
SDATA
SDATA
SDATA
SCK
SCK
SCK
SL
SL
SL
Address
A0 A1 A2
0
1
0
1
0
t
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
t
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK
DS
DS
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
FALLING EDGES.
ONE ADDRESS AT A TIME.
0
0
1
1
0
RNW
RNW
RNW
0
1
0
1
0
0
0
0
1
t
t
A0
0
LS
LS
2
A0
A0
t
t
A1
DH
DH
0
3
D0
Channel Select
CCD/AUX
LSB
LSB
0
LSB
Should be set to one.
A1
A1
0
4
0
A2
5
A2
D1
0
D0
6
TEST
TEST
0
0
D1
7
OPERATION
Table I. Internal Register Map
D2
Power-Down
Modes
0
11 BITS
D2
D0
D0
8
t
DV
D3
9
CDS Gain Clock Polarity Select for
D1
D1
On/Off
...
D3
...
D10
D2
D2
16
Data Bits
D0
17
D4
Software OB Clamp 0
Reset
SHP/SHD/CLP/DATA
D3
D3
D1
18
D4
D4
AGC GAIN
D2
10 BITS
19
D5
On/Off
MSB
D3
20
D5
D5
...
...
D6
D6
D9
26
D6
X
CLAMP LEVEL
D0
D7
D7
27
8 BITS
...
...
D8
D8
D7
1
MSB
0
X
D7
34
D9
D0
D9
CONTROL
35
t
t
10 BITS
LH
LH
...
...
D8
0
X
0
X
...
D10
D10
D9
44
D9
0
MSB
X
Three-
X
State
D10
0
X
X
X
X