AD9844AJSTRL Analog Devices Inc, AD9844AJSTRL Datasheet - Page 12

• Manufacturer Part Number: AD9844AJSTRL
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9844AJSTRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT DESCRIPTION AND OPERATION
The AD9844A signal processing chain is shown in Figure 11.
Each processing step is essential in achieving a high-quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a
dc-restore circuit is used with an external 0.1 µF series-coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V single supply of
the AD9844A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (t
propagation delays.
The CDS stage has a default gain of 4 dB, but uses a unique
architecture that allows the CDS gain to be varied. Using the
CDS Gain Register, the gain is programmable from –2 dB to
+10 dB in 64 steps, using two’s complement coding. The CDS
Gain curve is shown in Figure 12. To change the gain of the
CDS using the CDS Gain Register, the Control Register bit D3
must be set high (CDS Gain Enabled). The default gain setting
when bit Control Register Bit D3 is low (CDS Gain Disabled) is
4 dB. See Tables V and VI for more details.
A CDS gain of 4 dB provides some front-end signal gain and
improves the overall signal-to-noise ratio. This gain setting
works very well in most applications, and the CCD-Mode
Specifications use this default gain setting. However, the CDS
gain may be varied to optimize the AD9844A operation in a
particular application. Increased CDS gain can be useful with
low output level CCDs, while decreased CDS gain allows the
AD9844A to accept CCD signal swings greater than 1 V p-p.
Table VII summarizes some example CDS gain settings for
different maximum signal swings. The CDS Gain Register may
also be used “on the fly” to provide a +6 dB boost or –6 dB
attenuation when setting exposure levels. It is best to keep the
CDS output level from exceeding 1.5 V~1.6 V.
AD9844A
0.1 F
CLPDM
CCDIN
DC RESTORE
ID
) of 3 ns is caused by internal
CDS
6
–2dB TO +10dB
INPUT OFFSET
CLAMP
REGISTER
CDS GAIN
REGISTER
VGA GAIN
VGA
2dB TO 36dB
10
Max Input Signal
250 mV p-p
500 mV p-p
800 mV p-p
1 V p-p
1.25 V p-p
1.5 V p-p
8-BIT
DAC
(100000)
10
-2
8
6
4
2
0
32
FILTERING
DIGITAL
Table VII. Example CDS Gain Settings
OPTICAL BLACK
40
INTERNAL
CLAMP
12-BIT
V
ADC
REF
48
2V FULL SCALE
Recommended
Gain Range
8 to 10 dB
6 to 8 dB
4 to 6 dB
2 to 4 dB
0 to 2 dB
–2 to 0 dB
CDS GAIN REGISTER CODE
CLAMP LEVEL
56
REGISTER
0 TO 255 LSB
8
0
12
8
Register Code Range
21 to 31
10 to 21
63 to 10
53 to 63
42 to 53
32 to 42
DOUT
CLPOB
16
24
(011111)
31