AD9844AJSTRL Analog Devices Inc, AD9844AJSTRL Datasheet - Page 7

• Manufacturer Part Number: AD9844AJSTRL
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9844AJSTRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9844A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level
1, 1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
EQUIVALENT INPUT CIRCUITS
THREE-
STATE
DATA
330
DVDD
DVSS
DVDD
DVSS
DRVDD
DRVSS
DOUT
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
ADC. For the AD9844A, 1 LSB is 0.5 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9844A’s power supply. The PSR specification is calcu-
lated from the change in the data outputs for a given step
change in the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9844A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
RNW
N
ACVDD
ACVSS
codes) when N is the bit resolution of the
DVDD
DVSS
DATA OUT
DATA IN
DVSS
ACVSS
AD9844A
330
DVDD
DVSS