AD9844AJSTRL Analog Devices Inc, AD9844AJSTRL Datasheet - Page 15

• Manufacturer Part Number: AD9844AJSTRL
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9844AJSTRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

APPLICATIONS INFORMATION
The AD9844A is a complete Analog Front End (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 16, the CCD image (pixel) data is buffered and sent to
the AD9844A analog input through a series input capacitor. The
AD9844A performs the dc restoration, CDS, gain adjustment,
black level correction, and analog-to-digital conversion. The
AD9844A’s digital output data is then processed by the image
processing ASIC. The internal registers of the AD9844A—used to
control gain, offset level, and other functions—are programmed
by the ASIC or microprocessor through a 3-wire serial digital
interface. A system timing generator provides the clock signals
for both the CCD and the AFE.
Internal Power-On Reset Circuitry
After power-on, the AD9844A will automatically reset all inter-
nal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset opera-
tion is completed. Pin 43 (formerly RSTB on the AD9843
non-A) is no longer used for the reset operation. Toggling Pin
43 in the AD9844A will have no effect.
V-DRIVE
CCD
V
OUT
BUFFER
0.1 F
TIMING
CCD
CCDIN
GENERATOR
AD9844A
TIMING
REGISTER
CDS/CLAMP
TIMING
Grounding and Decoupling Recommendations
As shown in Figure 17, a single ground plane is recommended
for the AD9844A. This ground plane should be as continu-
ous as possible, particularly around Pins 25 through 39. This will
ensure that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins
and their respective ground pins. All decoupling capacitors
should be located as close as possible to the package pins. A
single clean power supply is recommended for the AD9844A, but
a separate digital driver supply may be used for DRVDD (Pin
13). DRVDD should always be decoupled to DRVSS (Pin 14),
which should be connected to the analog ground plane. Advan-
tages of using a separate digital driver supply include using a
lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing
digital power dissipation, and reducing potential noise coupling.
If the digital outputs (Pins 3–12) must drive a load larger than
20 pF, buffering is recommended to reduce digital code transi-
tion noise. Alternatively, placing series resistors close to the
digital output pins may help reduce noise.
ADC
DATA
OUT
OUTPUTS
INTERFACE
DIGITAL
SERIAL
DIGITAL IMAGE
PROCESSING
ASIC
AD9844A