AD9847AKST Analog Devices Inc, AD9847AKST Datasheet - Page 18

• Manufacturer Part Number: AD9847AKST
• Description: IC CCD SIGNAL PROC 10BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9847AKST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 40MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7/3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9847
HORIZONTAL CLAMPING AND BLANKING
The AD9847’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. As with the vertical
timing generation, individual sequences are defined for each
signal and are then organized into multiple regions during image
readout. This allows the dark pixel clamping and blanking patterns
to be changed at each stage of the readout, in order to accom-
modate different image transfer timing and high speed line shifts.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 9. These three signals are indepen-
dently programmed using the registers in Table IV. SPOL is the
start polarity for the signal, and TOG1 and TOG2 are the first
Register Name
SPOL
TOG1
TOG2
Register Name
HBLKMASK
HBLKTOG1
HBLKTOG2
CLPOB
CLPDM
HBLK
PBLK
HD
HD
NOTES
PROGRAMMABLE SETTINGS:
(1) FIRST TOGGLE POSITION = START OF BLANKING
(2) SECOND TOGGLE POSITION = END OF BLANKING
(1)
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
1b
12b
12b
Length
1b
12b
12b
Length
(1)
(2)
Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters
Range
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Range
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
BLANK
CLAMP
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
(2)
(3)
Figure 9. Clamp and Preblank Pulse Placement
Table V. HBLK Individual Sequence Parameters
Description
Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
Description
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
–18–
and second toggle positions of the pulse. All three signals are
active low and should be programmed accordingly. Up to four
individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 10 is similar to
CLPOB, CLPDM, and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and the stop positions of the blanking period. Additionally, there
is a polarity control, HBLKMASK, that designates the polarity of
the horizontal clock signals H1–H4 during the blanking period.
Setting HBLKMASK high will set H1 = H3 = low and H2 =
H4 = high during the blanking, as shown in Figure 11. Up to
four individual sequences are available for HBLK.
BLANK
CLAMP
. . .
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REV. A