DS92LV3221TVS/NOPB National Semiconductor, DS92LV3221TVS/NOPB Datasheet - Page 14

• Manufacturer Part Number: DS92LV3221TVS/NOPB
• Description: IC SERIALIZER LVDS 32BIT 64TQFP
• Manufacturer: National Semiconductor

Specifications of DS92LV3221TVS/NOPB

• Function: Serializer
• Data Rate: 1.6Gbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 32
• Number Of Outputs: 2
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV3221TVS

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Functional Description
The DS92LV3221 Serializer (SER) and DS92LV3222 Dese-
rializer (DES) chipset is a flexible SER/DES chipset that
translates a 32-bit parallel LVCMOS data bus into 2 pairs of
LVDS serial links with embedded clock. The DS92LV3221
serializes the 32-bit wide parallel LVCMOS word into two
high-speed LVDS serial data streams with embedded clock,
scrambles and DC Balances the data to support AC coupling
and enhance signal quality. The DS92LV3222 receives the
dual LVDS serial data streams and converts it back into a 32-
bit wide parallel data with a recovered clock. The dual LVDS
serial data stream reduces cable size, the number of connec-
tors, and eases skew concerns.
Parallel clocks between 20 MHz to 50 MHz are supported.
The embedded clock LVDS serial streams have an effective
data payload of 640 Mbps (20MHz x 32-bit) to 1.6 Gbps
(50MHz x 32- bit). The SER/DES chipset is designed to trans-
mit data over long distances through standard twisted pair
(TWP) cables. The differential inputs and outputs are inter-
nally terminated with 100 ohm resistors to provide source and
load termination, minimize stub length, to reduce component
count and further minimize board space.
The DES can attain lock to a data stream without the use of
a separate reference clock source; greatly simplifying system
complexity and reducing overall cost. The DES synchronizes
to the SER regardless of data pattern, delivering true auto-
matic “plug-and-lock” performance. It will lock to the incoming
serial stream without the need of special training patterns or
special sync characters. The DES recovers the clock and data
by extracting the embedded clock information, deskews the
serial data channels and then deserializes the data. The DES
also monitors the incoming clock information, determines lock
status, and asserts the LOCK output high when lock occurs.
In addition the DES also supports an optional AT-SPEED
BIST (Built In Self Test) mode, BIST error flag, and LOCK
status reporting pin. The SER and the DES have a power
down control signal to enable efficient operation in various
applications.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically provides a clock alignment and
deskew function without the need for any special training pat-
terns. During the locking phase, the embedded clock infor-
mation is recovered on all channels and the serial links are
internally synchronized, de-skewed, and auto aligned. The
internal CDR circuitry will dynamically compensate for up to
0.4 times the parallel clock period of per channel phase skew
(channel-to-channel) between the recovered clocks of the se-
rial links. This provides skew phase tolerance from mismatch-
es in interconnect wires such as PCB trace routing, cable pair-
to-pair length differences, and connector imbalances.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the in-
puts TxIN0–TxIN31 are latched into the encoder block. Data
is clocked into the SER by the TxCLKIN input. The edge of
TxCLKIN used to strobe the data is selectable via the R_FB
(SER) pin. R_FB (SER) high selects the rising edge for clock-
ing data and low selects the falling edge. The SER outputs
(TxOUT[1:0]+/-) are intended to drive a AC Coupled point-to-
point connections.
The SER latches 32-bit parallel data bus and performs sev-
eral operations to it. The 32-bit parallel data is internally
encoded and sequentially transmitted over the two high-
speed serial LVDS channels. For each serial channel, the
SER transmits 20 bits of information per payload to the DES.
14
This results in a per channel throughput of 400 Mbps to 1.0
Gbps (20 bits x clock rate).
When all of the DES channels obtain lock , the LOCK pin is
driven high and synchronously delivers valid data and recov-
ered clock on the output. The DES locks to the clock, uses it
to generate multiple internal data strobes, and then drives the
recovered clock to the RxCLKOUT pin. The recovered clock
(RxCLKOUT) is synchronous to the data on the RxOUT[31:0]
pins. While LOCK is high, data on RxOUT[31:0] is valid. Oth-
erwise, RxOUT[31:0] is invalid. The polarity of the RxCLK-
OUT edge is controlled by its R_FB (DES) input. RxOUT
[31:0], LOCK and RxCLKOUT outputs will each drive a max-
imum of 8 pF load. REN controls TRI-STATE® for RxOUT0–
RxOUT31 and the RxCLKOUT pin on the DES.
RESYNCHRONIZATION
In the absence of data transitions on one of the channels into
the DES (e.g. a loss of the link), it will automatically try to
resynchronize and re-establish lock using the standard lock
sequence on the master channel (Channel 0). For example,
if the embedded clock is not detected one time in succession
on either of the serial links, the LOCK pin is driven low. The
DES then monitors the master channel for lock, once that is
obtained, the second channel is locked and aligned. The logic
state of the LOCK signal indicates whether the data on Rx-
OUT is valid; when it is high, the data is valid. The system
may monitor the LOCK pin to determine whether data on the
RxOUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the SER
and DES may use to reduce power when no data is being
transferred. The respective PDB pins are used to set each
device into power down mode, which reduces supply current
into the µA range. The SER enters Powerdown when the SER
PDB pin is driven low. In Powerdown, the PLL stops and the
outputs go into TRI-STATE®, disabling load current and re-
ducing current supply. To exit Powerdown, SER PDB must
be driven high. When the SER exits Powerdown, its PLL must
lock to TxCLKIN before it is ready for sending data to the DES.
The system must then allow time for the DES to lock before
data can be recovered.
The DES enters Powerdown mode when DES PDB is driven
low. In Powerdown mode, the PLL’s stop and the outputs en-
ter TRI-STATE®. To bring the DES block out of the Power-
down state, the system drives DES PDB high. Both the SER
and DES must relock before data can be transferred from
Host and received by the Target. The DES will startup and
assert LOCK high when it is locked to the embedded clocks.
See also
TRI-STATE®
For the SER, TRI-STATE® is entered when the SER PDB pin
is driven low. This will TRI-STATE® the driver output pins on
TxOUT[1:0]+/-.
When you drive the REN or DES PDB pin low, the DES output
pins (RxOUT[31:0]) and RxCLKOUT will enter TRI-STATE®.
The LOCK output remains active, reflecting the state of the
PLL. The DES input pins are high impedance during receiver
Powerdown (DES PDB low) and power-off (VDD = 0V). See
also
TRANSMIT PARALLEL DATA AND CONTROL INPUTS
The DS92LV3221 operates on a core supply voltage of 3.3V
with an optional digital supply voltage for 1.8V, low-swing, in-
put support. The SER single-ended (32-bit parallel data and
control inputs) pins are 1.8V and 3.3V LVCMOS logic level
Figure
Figure
11.
11.