DS92LV3221TVS/NOPB National Semiconductor, DS92LV3221TVS/NOPB Datasheet
DS92LV3221TVS/NOPB
Specifications of DS92LV3221TVS/NOPB
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DS92LV3221TVS/NOPB Summary of contents
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... A built-in AT- SPEED BIST feature validates link integrity and may be used for system diagnostics. Block Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation DS92LV3221/DS92LV3222 Features ■ ...
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DS92LV3221 Pin Diagram www.national.com FIGURE 1. DS92LV3221 Pin Diagram— Top View 2 30105730 ...
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DS92LV3221 Serializer Pin Descriptions Pin # Pin Name I/O, Type LVCMOS PARALLEL INTERFACE PINS 10–8, TxIN[31:29], I, LVCMOS 5–1, TxIN[28:24], 64–57, TxIN[23:16], 52–51, TxIN[15:14], 48–44. TxIN[13:9], 41–33 TxIN[8:0] 11 TxCLKIN I, LVCMOS CONTROL AND CONFIGURATION PINS 12 PDB I, LVCMOS ...
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DS92LV3222 Pin Diagram www.national.com FIGURE 2. DS92LV3222 Pin Diagram — Top View 4 30105731 ...
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DS92LV3222 Deserializer Pin Descriptions Pin # Pin Name I/O, Type LVCMOS PARALLEL INTERFACE PINS 5–7, RxOUT[31:29], O, LVCMOS Deserializer Parallel Interface Data Output Pins. 10–14, RxOUT[28:24], 19–25, RxOUT[23:17], 28–32, RxOUT[16:12], 33–39, RxOUT[11:5], 42–46 RxOUT[4:0] 4 RxCLKOUT O, LVCMOS Deserializer Recovered ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage LVCMOS Output Voltage LVDS Deserializer Input Voltage LVDS Driver Output Voltage Junction Temperature Storage Temperature Lead Temperature ...
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Symbol Parameter I Output Short Circuit Current OS I TRI-STATE® Output Current OZ R Output Termination T SERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS I Serializer (Tx) Total Supply Current DDTD (includes load current) ...
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Serializer Input Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t TxCLKIN Period CIP t TxCLKIN High Time CIH t TxCLKIN Low Time TCIL t TxCLKIN Transition Time CIT t TxCLKIN Jitter ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Receiver Output Clock Period ROCP t RxCLKOUT Duty Cycle RODC t LVCMOS Low-to-High Transition ROTR Time t LVCMOS High-to-Low Transition ROTF Time t RxOUT[31:0] ...
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AC Timing Diagrams and Test Circuits www.national.com FIGURE 3. Serializer LVDS Transition Times FIGURE 4. Serializer Input Clock Transition Time FIGURE 5. Serializer Setup/Hold and High/Low Times FIGURE 6. Serializer Propagation Delay 10 30105732 30105745 30105749 30105747 ...
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FIGURE 7. Serializer PLL Lock Time FIGURE 8. Deserializer LVCMOS Output Transition Time FIGURE 9. Deserializer Setup and Hold times FIGURE 10. Deserializer Propagation Delay 11 30105733 30105748 30105734 30105746 www.national.com ...
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FIGURE 11. Deserializer PLL Lock Time and PDB TRI-STATE® Delay FIGURE 12. Deserializer TRI_STATE Test Circuit and Timing www.national.com 12 30105735 30105736 ...
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FIGURE 13. Serializer Jitter Transfer FIGURE 14. Serializer V Test Circuit Diagram OD FIGURE 15. LVDS Deserializer Input Skew 13 30105751 30105737 30105738 www.national.com ...
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Functional Description The DS92LV3221 Serializer (SER) and DS92LV3222 Dese- rializer (DES) chipset is a flexible SER/DES chipset that translates a 32-bit parallel LVCMOS data bus into 2 pairs of LVDS serial links with embedded clock. The DS92LV3221 serializes the 32-bit ...
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IOVDD input supply rail. If 1.8V is required, the IOVDD pin must be connected to a 1.8V supply rail. Also when power is applied to the trans- mitter, IOVDD pin must be applied before ...
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Under the BIST mode, the DES parallel outputs on RxOUT [31:0] are multiplexed to represent BIST status indicators. The pass/fail status of the BIST is represented by a Pass flag along with an Error counter. The Pass flag output is ...
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FIGURE 17. BIST Diagram for Different Bit Error Cases TYPICAL APPLICATION CONNECTION Figure 18 shows a typical application of the DS92LV3221 Se- rializer (SER). The differential outputs utilize 100nF coupling capacitors to the serial lines. Bypass capacitors are placed near ...
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Figure 19 shows a typical application of the DS92LV3222 Deserializer (DES). The differential inputs utilize 100nF cou- pling capacitors in the serial lines. Bypass capacitors are www.national.com FIGURE 18. DS92LV3221 Typical Connection Diagram placed near the power supply pins. A ...
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RxCLKOUT. The REN signal is not used and is tied High also. Configuration pins for the typical application are shown for DES: • PDB – Power Down Control Input – Connect to host or tie HIGH FIGURE ...
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Applications Information TRANSMISSION MEDIA The SER and DES are used in AC-coupled point-to-point configurations, through a PCB trace, or through twisted pair cables. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and connectors that have ...
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Typical Performance Characteristics The waveforms below illustrate the typical performance of the DS92LV3221. The SER was given a PCLK and configured as described below each picture. In all of the pictures the SER was configured with BISTEN pin set to ...
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Physical Dimensions Ordering Information NSID DS92LV3221TVS 64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch DS92LV3221TVSX 64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch DS92LV3222TVS 64-Lead TQFP style, 10.0 X 10.0 X 1.0 ...
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Notes 23 www.national.com ...
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