DS92LV3221TVS/NOPB National Semiconductor, DS92LV3221TVS/NOPB Datasheet - Page 17

• Manufacturer Part Number: DS92LV3221TVS/NOPB
• Description: IC SERIALIZER LVDS 32BIT 64TQFP
• Manufacturer: National Semiconductor

Specifications of DS92LV3221TVS/NOPB

• Function: Serializer
• Data Rate: 1.6Gbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 32
• Number Of Outputs: 2
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV3221TVS

TYPICAL APPLICATION CONNECTION
Figure 18
rializer (SER). The differential outputs utilize 100nF coupling
capacitors to the serial lines. Bypass capacitors are placed
near the power supply pins. A system GPO (General Purpose
Output) controls the PDB and BISTEN pins. In this application
the R_FB (SER) pin is tied Low to latch data on the falling
edge of the TxCLKIN. In this application the link is short,
therefore the VSEL pin is tied LOW for the standard output
swing level. The Pre-emphasis input utilizes a resistor to
ground to set the amount of pre-emphasis desired by the ap-
plication.
Configuration pins for the typical application are shown for
SER:
•
PDB – Power Down Control Input – Connect to host or tie
HIGH (always ON)
shows a typical application of the DS92LV3221 Se-
FIGURE 17. BIST Diagram for Different Bit Error Cases
17
•
•
•
•
There are eight power pins for the device. These may be
bussed together on a common 3.3V plane (3.3V LVCMOS I/
O interface). If 1.8V input swing level for parallel data and
control pins are required, connect the IOVDD pin to 1.8V. At
a minimum, eight 0.1uF capacitors should be used for local
bypassing.
BISTEN – Mode Input - tie LOW if BIST mode is not used,
or connect to host
VSEL – tie LOW for normal VOD (application dependant)
PRE – Leave open if not required (have a R pad option on
PCB)
RSVD1 & RSVD2 – tie LOW
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