DS92LV3221TVS/NOPB National Semiconductor, DS92LV3221TVS/NOPB Datasheet - Page 15

• Manufacturer Part Number: DS92LV3221TVS/NOPB
• Description: IC SERIALIZER LVDS 32BIT 64TQFP
• Manufacturer: National Semiconductor

Specifications of DS92LV3221TVS/NOPB

• Function: Serializer
• Data Rate: 1.6Gbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 32
• Number Of Outputs: 2
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV3221TVS

compatible and is configured through the IOVDD input supply
rail. If 1.8V is required, the IOVDD pin must be connected to
a 1.8V supply rail. Also when power is applied to the trans-
mitter, IOVDD pin must be applied before or simultaneously
with other power supply pins (3.3V). If 1.8V input swing is not
required, this pin should be tied to the common 3.3V rail. Dur-
ing normal operation, the voltage level on the IOVDD pins
must not change.
PRE-EMPHASIS
The SER LVDS Line Driver features a Pre-Emphasis function
used to compensate for extra long or lossy transmission me-
dia. The same amount of Pre-Emphasis is applied on all of
the differential output channels. Cable drive is enhanced with
a user selectable Pre-Emphasis feature that provides addi-
tional output current during transitions to counteract cable
loading effects. The transmission distance will be limited by
the loss characteristics and quality of the media.
To enable the Pre-Emphasis function, the “PRE” pin requires
one external resistor (Rpre) to VSS (GND) in order to set the
pre-emphasized current level. Options include:
1.
2.
Values of the Rpre Resistor should be between 12K Ohm and
100K Ohm. Values less than 6K Ohm should not be used. The
amount of Pre-Emphasis for a given media will depend on the
transmission distance and Fmax of the application. In gener-
al, too much Pre-Emphasis can cause over or undershoot at
the receiver input pins. This can result in excessive noise,
crosstalk, reduced Fmax, and increased power dissipation.
For shorter cables or distances, Pre-Emphasis is typically not
be required. Signal quality measurements should be made at
the end of the application cable to confirm the proper amount
of Pre-Emphasis for the specific application.
The Pre-Emphasis circuit increases the drive current to I =
48 / (R
is increased by an additional 3.2 mA. To calculate the ex-
pected increase in V
ohms. So for the case of R
V
the current is controlled to one bit by time. If more than one
bit value is repeated in the next cycle(s), the Pre-Emphasis
current is turned off (back to the normal output current level)
for the next bit(s). To boost high frequency data and pre-
equalize teh data patternreduce ISI (Inter-Symbol Interfer-
ence) improving the resulting eye pattern.
V
The SER Line Driver Differential Output Voltage (V
nitude is selectable. Two levels are provided and are selected
by the VSEL pin. When this pin is LOW, normal output levels
are obtained. For most application set the VSEL pin LOW.
When this pin is HIGH, the output current is increased to dou-
ble the V
or high-loss interconnects.
V
VSEL Pin Setting
LOW
HIGH
OD
OD
OD
Normal Output (no Pre-emphasis) – Leave the PRE pin
open, include an R pad, do not populate.
Enhanced Output (Pre-emphasis enabled) – connect a
resistor on the PRE pin to Vss.
would be 3.2 mA x 50 Ohms = 160 mV. The duration of
SELECT
PRE
Control
OD
). For example if R
level. Use this setting only for extra long cables
OD
, multiply the increase in current by 50
Effect
Small V
Large V
PRE
PRE
= 15 kOhms, then the current
OD
= 15 kOhms, the boost to
OD
, typ 440 mV
, typ 850 mV
P-P
P-P
OD
) mag-
15
SERIAL INTERFACE
The serial links between the DS92LV3221 and the
DS92LV3222 are intended for a balanced 100 Ohm intercon-
nects. The links must be configured as an AC coupled inter-
face.
The SER and DES support AC-coupled interconnects
through an integrated DC balanced encoding/decoding
scheme. An external AC coupling capacitors must be placed,
in series, in the LVDS signal path. The DES input stage is
designed for AC-coupling by providing a built-in AC bias net-
work which sets the internal common mode voltage (VCM) to
+1.8V.
For the high-speed LVDS transmission, small footprint pack-
ages should be used for the AC coupling capacitors. This will
help minimize degradation of signal quality due to package
parasitics. NPO class 1 or X7R class 2 type capacitors are
recommended. 50 WVDC should be the minimum used for
best system-level ESD performance. The most common used
capacitor value for the interface is 100 nF (0.1 uF) capacitor.
One set of capacitors may be used for isolation. Two sets
(both ends) may also be used for maximum isolation of both
the SER and DES from cable faults.
The DS92LV3221 and the DS92LV3222 differential I/O’s are
internally terminated with 100 Ohm resistance between the
inverting and non-inverting pins and do not require external
termination. The internal resistance value will be between 90
ohm and 130 ohm. The integrated terminations improve sig-
nal integrity, reduce stub lengths, and decrease the external
component count resulting in space savings.
AT-SPEED BIST FEATURE
The DS92LV3221/ DS92LV3222 serial link is equipped with
built-in self-test (BIST) capability to support both system man-
ufacturing and field diagnostics. BIST mode is intended to
check the entire high-speed serial interface at full link-speed
without the use of specialized and expensive test equipment.
This feature provides a simple method for a system host to
perform diagnostic testing of both SER and DES. The BIST
function is easily configured through the SER BISTEN pin.
When the BIST mode is activated, the SER generates a
PRBS (pseudo-random bit sequence) pattern (2^7-1). This
pattern traverses each lane to the DES input. The
DS92LV3222 includes an on-chip PRBS pattern verification
circuit that checks the data pattern for bit errors and reports
any errors on the data output pins of the DES.
The AT-Speed BIST feature is enabled by setting the BISTEN
to High on SER. The BISTEN input must be High or Low for
4 or more TxCLKIN clock cycles in order to activate or deac-
tivate the BIST mode. An input clock signal for the Serializer
TxCLKIN must also be applied during the entire BIST opera-
tion. Once BIST is enabled, all the Serializer data inputs (TxIN
[31:0]) are ignored and the DES outputs (RxOUT[31:0]) are
not available. Next, the internal test pattern generator for each
channel starts transmission of the BIST pattern from SER to
DES. The DES BIST mode will be automatically activated by
this sequence. A maximum of 128 consecutives clock sym-
bols on DS92LV3222 DES is needed to detect BIST enable
function. The BIST is implemented with independent transmit
and receive paths for the two serial links. Each channel on the
DES will be individually compared against the expected bit
sequence of the BIST pattern.
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