DS92LV3221TVS/NOPB National Semiconductor, DS92LV3221TVS/NOPB Datasheet - Page 9

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DS92LV3221TVS/NOPB

Manufacturer Part Number
DS92LV3221TVS/NOPB
Description
IC SERIALIZER LVDS 32BIT 64TQFP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV3221TVS/NOPB

Function
Serializer
Data Rate
1.6Gbps
Input Type
LVCMOS
Output Type
LVDS
Number Of Inputs
32
Number Of Outputs
2
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS92LV3221TVS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS92LV3221TVS/NOPB
Manufacturer:
NSC
Quantity:
260
Part Number:
DS92LV3221TVS/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
t
t
t
t
t
t
t
t
t
t
t
t
TOL
t
ROCP
RODC
ROTR
ROTF
ROSC
ROHC
HZR
LZR
ZHR
ZLR
RD
RPLLS
LVSKR
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms at V
characterization and are not guaranteed.
Note 3: Current into a the device is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V
ΔV
Note 4: When the Serializer output is at TRI-STATE® the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: t
Symbol
JIT
OD
, V
TH
RPLLS
, V
TL
Receiver Output Clock Period
RxCLKOUT Duty Cycle
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
RxOUT[31:0] Setup to RxCLKOUT
RxOUT[31:0] Hold to RxCLKOUT
Data Output High to TRI-STATE®
Delay
Data Output Low to TRI-STATE®
Delay
Data Output TRI-STATE® to High
Delay
Data Output TRI-STATE® to Low
Delay
Deserializer Porpagation Delay –
Latency
Deserializer PLL Lock Time
Deserializer Input Jitter Tolerance
LVDS Differential Input Skew
Tolerance
is the time required by the Deserializer to obtain lock when exiting power-down mode.
which are differential voltages.
Parameter
t
Figure 9
C
(lumped load)
Figure 8
f = 50 MHz
Figure 11
f = 20 MHz
Figure 10
f = 50 MHz
20 MHz – 50 MHz
Figure 11
(Note
20 MHz – 50 MHz
Figure 15
ROCP
L
= 8pF
DD
= t
5)
= 3.3V, T
CIP
A
9
Conditions
= +25°C, and at the Recommended Operating Conditions at the time of product
Min
5.6
7.4
20
45
t
t
ROCP
ROCP
t
t
t
0.5 x
0.5 x
5.5 x
5.5 x
3.35
6.00
0.25
Typ
ROCP
ROCP
ROCP
3.2
3.5
50
5
5
5
5
+
+
128k x
t
t
0.4 x
Max
ROCP
ROCP
50
55
10
10
10
10
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