P82B715TD,112 NXP Semiconductors, P82B715TD,112 Datasheet
P82B715TD,112
Specifications of P82B715TD,112
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P82B715TD
P82B715TD
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P82B715TD,112 Summary of contents
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P82B715 2 I C-bus extender Rev. 08 — 9 November 2009 1. General description The P82B715 is a bipolar IC intended for application in I systems. While retaining all the operating modes and features of the I extension of the ...
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... NXP Semiconductors I Supply voltage range Clock speeds to at least 100 kHz and 400 kHz when other system delays permit I ESD protection exceeds 2500 V HBM per Mil. Std 883C-3015.7 and 400 V MM per JESD22-A115 (I/Os have diodes Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 3 ...
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... NXP Semiconductors 5. Block diagram Fig 1. 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Symbol n. GND n. P82B715_8 Product data sheet P82B715 SDA SCL Block diagram of P82B715 P82B715PN n. GND n.c. 002aad686 Pin configuration for DIP8 Pin description Pin Description 1 not connected ...
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... NXP Semiconductors 7. Functional description The P82B715 is a dual bidirectional logic signal device having unity voltage gain in both directions, but 10 current amplification in one direction that allows increasing the allowable I and requires no external directional control. It uses unidirectional analog current amplification to increase the current sink capability of I ...
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... NXP Semiconductors 7.2 Lx, Ly: buffered bus LDA or LCL On the special low-impedance or buffered line side, the corresponding output at the pins becomes the LDA data line or LCL clock line. 7 GND: positive and negative supply pins CC The power supply voltages at each P82B715 used in a system are normally nominally the same. If they differ by a signifi ...
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... NXP Semiconductors 2 8.1 I C-bus systems As in standard I levels on the buffered bus. (The standard open-collector configuration is retained.) The value and number of pull-up resistors used is flexible and depends on the system requirements and designer preferences. If P82B715 ICs are to be permanently connected into a system it could be configured with only one pull-up resistor on the buffered bus and none on the I design will be simplifi ...
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... NXP Semiconductors This equivalent capacitance is the sum of the capacitance on the buffered bus plus 10 times the sum of the capacitances on all the connected I value should not exceed 4 nF. The single buffered bus pull-up resistor is then calculated to achieve the rise time requirement and it then provides the pull-up for the buffered bus and ...
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... NXP Semiconductors The P82B715 has a static sink rating Lx. The requirement is that the pull-up on the buffered bus, in parallel with all other pull-ups that it is indirectly pulling LOW on Sx pins of other P82B715 ICs, will not cause this 30 mA limit to be exceeded. The minimum pull-up resistance ...
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... NXP Semiconductors 3.3 V ShMM Calculations to ensure rise time is met on each bus section: total capacitance C1 Fig 8. Figure 8 In this example the total system capacitance is 2800 pF, but it is distributed over 18 different bus sections and no section has a capacitance greater than 200 pF. If every individual bus section is designed to rise at least as fast as the IPMB requirement, then when any driver releases the bus, all bus sections will rise together and no amplifi ...
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... NXP Semiconductors 8.2 Quick design-in point-to-point/multi-point circuit information for 5 V bus With many variables (cable length/capacitance, local capacitive loading on each I bus voltages, and bus speed), optimizing a design can be complex and requires significant study of the application note information. The following circuit and simplified ...
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... NXP Semiconductors • The 300 ns bus fall time, and the Standard-mode I 400 pF, must also be observed. If the 400 pF limit is observed the fall time limit will be met. Allocate about 266 pF, for the cable bus loading as it will appear at the Sx/Sy pins. The 10 gain of P82B715 allows the loading at Lx/ times the load at Sx/Sy, so 2660 pF maximum ...
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... NXP Semiconductors Figure 10 on the P82B715 Sx/Sy I/O. Notice that the offset is small and the static levels remain under 0.4 V. Coupling of SDA to SCL is negligible when SCL is LOW but slight cross-coupling of SCL to SDA is visible when SDA is HIGH and therefore higher impedance. The waveforms are very clean and will easily support all available I masters and slaves ...
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... NXP Semiconductors 9. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol bus V buff I P tot T stg T amb [1] Voltages with respect to GND. The bus voltages quoted are DC voltages and are allowed to be exceeded during any negative transient undershoot that may be generated by normal operation of P82B715, P82B96 or PCA9600 when any of those parts are driving long PCB traces, wiring or cables ...
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... NXP Semiconductors Table 5. Characteristics …continued unless otherwise specified. amb CC Symbol Parameter Input currents input current from I C-bus input current from buffered bus leakage current on buffered bus Impedance transformation Z /Z input/output impedance in out Buffer delay times t time delay to V voltage rise/fall delay ...
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... NXP Semiconductors 12. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Soldering of through-hole mount packages 14.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. ...
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... NXP Semiconductors 14.4 Package related soldering information Table 8. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. ...
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... NXP Semiconductors 16. Revision history Table 10. Revision history Document ID Release date P82B715_8 20091109 • Modifications: Table 4 “Limiting P82B715_7 20080529 P82B715_6 20031202 (9397 750 12452) P82B715_5 20030220 (9397 750 11094) P82B715_4 20010306 (9397 750 08163) P82B715_8 Product data sheet Data sheet status ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 2 7.1 Sx, Sy: I C-bus SDA or SCL . . . . . . . . . . . . . . . 4 7.2 Lx, Ly: buffered bus LDA or LCL ...