P82B715TD,112 NXP Semiconductors, P82B715TD,112 Datasheet - Page 9

• Manufacturer Part Number: P82B715TD,112
• Description: IC I2C BUS EXTENDER 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Bus Extenderr

Specifications of P82B715TD,112

• Package / Case: 8-SOIC (3.9mm Width)
• Tx/rx Type: I²C Logic
• Delay Time: 250ns
• Capacitance - Input: 3000pF
• Voltage - Supply: 4.5 V ~ 12 V
• Current - Supply: 22mA
• Mounting Type: Surface Mount
• Logic Family: P82B
• Number Of Lines (input / Output): 1 / 1
• Propagation Delay Time: 250 ns
• Operating Supply Voltage: 4.5 V to 12 V
• Power Dissipation: 300 mW
• Operating Temperature Range: - 40 C to + 85 C
• Logic Type: I2C Bus Extender
• Mounting Style: SMD/SMT
• Number Of Input Lines: 1
• Number Of Output Lines: 1
• Output Current: 60 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3981-5; 935154770112; P82B715TD; P82B715TD

NXP Semiconductors
P82B715_8
Product data sheet
Figure 8
In this example the total system capacitance is 2800 pF, but it is distributed over 18
different bus sections and no section has a capacitance greater than 200 pF.
If every individual bus section is designed to rise at least as fast as the IPMB requirement,
then when any driver releases the bus, all bus sections will rise together and no amplifiers
in the P82B715s will be activated or, if one is activated, it can only slow the system bus
rise to its own rate and that has been designed to meet the requirement.
It is then only necessary to calculate the equivalent static bus pull-up loading and to
ensure that it exceeds the specification requirement. The calculated loadings meet the
requirements.
Note that in this example only one of the four IPMB lines is shown and the usual switching
arrangements for isolating or cross-connecting bus lines are not shown. The typical offset
(increase in the bus LOW level) measured between any two Sx points in this system is
below 100 mV.
Fig 8.
3.3 V
ShMM
Calculations to ensure rise time is met on each bus section:
total capacitance C1
shows P82B715 in an analog radial IPMB shelf application.
Calculation of static loading at ShMM buffer and each FRU:
Loading on ShMM buffer = R1 {10 (R2 R3/16)} = 3.5 k
Loading on each FRU = R3 {10 (R1 R2 R3/15)} = 3.76 k
Typical arrangement and calculations for an IPMB analog radial shelf
R1 =
effective capacitance
ShMM buffer pull-up
at ShMM buffer
ShMM buffer
BUFFER
40 pF
P82B715
1 s
strays
= 25 k
Rev. 08 — 9 November 2009
common Lx node
R1
C1
10 pF
20 pF
10 pF
40 pF
Sx
Lx
C2
total capacitance C2
trace capacitance
R2
R2 =
effective capacitance
at common Lx node
Lx common pull-up
17
200 pF
Lx
Lx
Lx
P82B715
1 s
16
1
2
Sx
Sx
Sx
= 5 k
170 pF
200 pF
30 pF
R3
R3
R3
C3
C3
C3
radial traces
radial trace/connector
total capacitance C3
at average radial trace
R3 =
effective capacitance
radial trace pull-up
160 pF
P82B715
1 s
1
P82B715
© NXP B.V. 2009. All rights reserved.
I
2
C-bus extender
FRU
BUFFER
BUFFER
BUFFER
= 6.2 k
FRU 16
FRU 1
FRU 2
002aad708
125 pF
160 pF
25 pF
10 pF
C
C
C
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