SSTUB32S869BHLF IDT, Integrated Device Technology Inc, SSTUB32S869BHLF Datasheet - Page 11

• Manufacturer Part Number: SSTUB32S869BHLF
• Description: IC REGIST BUFF 14BIT DDR2 150BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Bufferr

Specifications of SSTUB32S869BHLF

• Tx/rx Type: LVCMOS
• Delay Time: 3.0ns
• Capacitance - Input: 3.5pF
• Voltage - Supply: 1.7 V ~ 1.9 V
• Mounting Type: Surface Mount
• Package / Case: *
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 28
• High Level Output Current: -16mA
• Low Level Output Current: 16mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 340(Min)MHz
• Mounting: Surface Mount
• Pin Count: 150
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant

1203—04/11/06
T
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - The vendor must supply this value for full device description.
Electrical Characteristics - DC
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
SYMBOL
A
= 0 - 70°C; V
V
I
V
V
PARAMETER
I
DDD
C
DD
I
OH
OL
IK
I
i
dV/dt_∆
dV/dt_r
dV/dt_f
All Inputs
Standby (Static)
Operating (Static)
Dynamic operating
(clock only)
Dynamic Operating
(per each data input)
Input capacitance,
D
Input capacitance,
DCS#
Input capacitance,
CK and CK# inputs
Input capacitance,
RESET# input
Data Inputs
CLK and CLK#
RESET#
n
, PAR_IN inputs
PARAMETERS
1
DD
n
= 2.5 +/-0.2V, V
2
MIN
1
1
V
I
I
I
I
I
V
RESET# = GND
V
RESET# = V
RESET# = V
V
CLK and CLK# switching
50% duty cycle.
RESET# = V
V
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
V
V
V
V
V
V
V
I
OH
OH
OL
OL
DD
DDQ
I
I
I
I
I
I
ICR
I
I
ICR
I
= -18mA
= V
= V
= V
= V
= V
= V
= V
= V
= V
= 100µA
= 16mA
= -100µA
= -16mA
= 1.8V ± 0.1V
= 0.9V; V
= 1.25V, V
=2.5 +/-0.2V; (unless otherwise stated)
IH(AC)
REF
DD
IH(AC)
IH(AC)
REF
REF
DD
DDQ
or GND
or GND
±350mV
± 250 mV
± 250 mV
or GND
CONDITIONS
or V
or V
or V
DD
DD
DD
I(PP)
,
,
IL(AC)
I(PP)
IL(AC)
IL (AC)
MAX
4
4
1
= 600 mV
= 360mV
,
,
,
I
11
O
= 0
V
1.7V
1.7V
1.7V
1.7V
1.9V
1.9V
1.8V
1.8V
DDQ
UNIT
V/ns
V/ns
V/ns
V
DDQ
Note 2
ICSSSTUB32S869B
Advance Information
MIN
1.2
2.5
2.5
2
2
2
- 0.2
TYP
TBD
TBD
TBD
2.5
Note 2
MAX
-1.2
0.2
0.5
0.2
3.5
3.5
±5
3
3
3
MHz/data
µA/ clock
µ/clock
UNITS
MHz
mA
µA
µA
pF
pF
pF
pF
pF
V