PCA9545AD,118 NXP Semiconductors, PCA9545AD,118 Datasheet - Page 10

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PCA9545AD,118

Manufacturer Part Number
PCA9545AD,118
Description
IC I2C SWITCH 4CH 20-SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9545AD,118

Applications
4-Channel I²C Switcher
Interface
I²C
Voltage - Supply
2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Package / Case
20-SOIC (7.5mm Width)
Mounting Type
Surface Mount
Logical Function
I2C Multiplexer
Configuration
1 x 4:1
Number Of Inputs
4
Number Of Outputs
1
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
5.5V
Power Dissipation
400mW
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
SO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1864-2
935275808118
PCA9545AD-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9545AD,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
7. Characteristics of the I
PCA9545A_45B_45C_7
Product data sheet
7.1 Bit transfer
7.2 START and STOP conditions
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see
Fig 10. Bit transfer
Fig 11. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
C-bus
S
Rev. 07 — 19 June 2009
Figure
4-channel I
11).
data valid
data line
stable;
Figure
2
C-bus switch with interrupt logic and reset
allowed
change
of data
PCA9545A/45B/45C
10).
STOP condition
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P
© NXP B.V. 2009. All rights reserved.
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