SCANSTA101SM/NOPB National Semiconductor, SCANSTA101SM/NOPB Datasheet - Page 11

• Manufacturer Part Number: SCANSTA101SM/NOPB
• Description: IC TEST MASTER LOW-VOLT 49FBGA
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM/NOPB

• Applications: Testing Equipment
• Interface: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 49-FBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *SCANSTA101SM; *SCANSTA101SM/NOPB; SCANSTA101SM

ductor SCAN Ease software does not allow PPI writes to the
TDI_SM memory.
Parallel Processor Interface
The overall function of the PPI is to receive the parallel data
from the processor; store the data in the appropriate register
or memory location; act on the data if the data are PPI control
data; provide status data back to the processor; and provide
a read path for result data to the processor. The PPI consists
of seven main blocks of logic. These blocks are the Edge De-
tector (ED), Processor Interface Controller (PIC), the Memo-
ry/Register Decoder (MRD), the Word/Long Word Converter
(WLWC), the Control Generator (CG), the Status/Interrupt
Generator (SIG) and the Flag Generator (FG).
WORD/LONG WORD CONVERTER
The Word/Long Word Converter (WLWC) has four 16-bit cap-
ture registers: a least significant/most significant (LS/MS)
word read capture register pair; and a LS/MS word write cap-
ture register pair.
Each register within the write register pair has a separate en-
able to allow for the necessary control to accomplish word to
long word conversions when in the 16-bit mode. In 32-bit
mode, these enables are driven simultaneously. A mux is
provided in front of the MS word write capture register to se-
lect between the 32-bit and 16-bit mode external bus.
Only one enable and a mux select is needed to control the
read capture register pair to accomplish the long word to word
conversions when in the 16- bit mode. In the 32-bit mode, the
mux selection doesn't change, so 32 bits are always driven.
A mux is on either side of the LS word read capture register.
The mux at the register output provides for selection between
the 32-bit and 16-bit mode. The mux at the register input is
for selection between register space and memory space.
All the control for this block is provided by the PIC and MRD
with the 16/32-bit mode enable coming from the Setup regis-
ter.
EDGE DETECTOR
The PPI module can support either an asynchronous or syn-
chronous processor interface. For an asynchronous interface,
the circuit initially synchronizes STB and CE to the system
clock, SCK, by pipelining these two signals through two flip-
flop stages and then performing an edge detection on STB
and CE. For a synchronous parallel processor interface, this
circuit just performs an edge detection. The outputs of this
circuit, one clock wide pulses indicating the detection of neg-
ative and positive edges, are used by the Processor Interface
Controller (PIC) state machine to start and to end a processor
access.
PROCESSOR INTERFACE CONTROLLER
The Processor Interface Controller (PIC) monitors the incom-
ing processor control signals and sets up the appropriate
internal control signals to move the data into memory or into
an internal register on a write or to move the data out of mem-
ory or out of an internal register on a read. The PIC edge
detects the CE and the STB to start the access. The PIC pro-
vides the control for the word to long word conversion in the
WLWC by controlling the three enables and the mux select
(READ_MSW) to the capture registers. The PIC also controls
when the internal read/write enable is issued to the memory
to complete the read/write operation. Timing for register and
memory read and write operations is described in
and
Figure
12.
Figure 11
11
MEMORY/REGISTER DECODER
The Memory/Register Decoder (MRD) contains all six index
registers (Index, Vector Index, Header/Trailer Index, Macro
Index, Sequencer Index and ScanBridge Support Index) and
four address registers (TDI_SM Address, TDO_SM Address,
Expected Address and Mask Address). On the PPI side, both
index and address registers are used to maintain pointers to
their respective memory spaces. The Index register sets val-
ues in all four address registers; i.e., writing to the Index
register sets all of the address registers. The value written to
each address register is the sum of its base address and the
value written to the Index register (the offset). All index and
address registers except the Index register auto-increment
with each access to the corresponding memory space.
The MRD provides the address decode to generate all the
control and status register enables for the CG and the SIG.
The MRD also provides the mux selects for the register or
memory selection for the read capture operation in the
WLWC.
CONTROL GENERATOR
The Control Generator includes the seven control registers:
the Start, Interrupt Control, Setup, Clock Divider, TDI_SM LF-
SR Exponent, TDI_SM LFSR LSB Seed, and TDI_SM LFSR
MSB Seed registers are included in this block. The CG issues
a strobe to the SSI when a write has been issued to the Start
or Setup registers so the SSI can react to the new control
data. The strobe is derived from edge detecting the enables
to the Start or Setup registers. The "new" data to the SSI are
the Use Sequencer bit and three Use Vector bits from the
Start register, and the TDO Default Value, TRST, ScanBridge
Support Initiate/Release, three-bit Sync Bit Length, and two
Test Loop-back bits from the Setup register.
STATUS/INTERRUPT GENERATOR
The Status/Interrupt Generator comprises the four status reg-
isters plus the logic to generate the interrupts and to clear the
interrupts on a read. The registers are the Status, Interrupt
Status, TDI_SM LFSR LSB Result and TDI_SM LFSR MSB
Result registers. The SIG receives the LFSR result and strobe
signal SSI_LFSR_EN from the SSI and captures the data in
the LSB and MSB registers. The SIG receives the compare
result bit value from the SSI along with the compare result bit
clear and the compare result bit load.
The SIG receives the 4 memory space flags from the FG
along with their associated load and clear signals so these
bits may be constantly updated. The half-full, half-empty, full
and empty flags are generated and updated regardless of the
states of their respective interrupt enables. The SIG also re-
ceives the four interrupt enables for the flags. The SIG also
receives the sequencer active and the three vector active sig-
nals from the SSI. These are also updated regardless of the
enable state.
If an interrupt enable is set then an interrupt will be generated.
If an interrupt occurs at the same time as the interrupt status
is being read, then the interrupt will be set after the read is
complete. All bits in the Interrupt Status register are cleared
when the register is read.
FLAG GENERATOR
The FG takes in the TDI_SM or TDO_SM pointer values from
the PPI address pointers, compares them and generates the
appropriate flags. If a flag condition has occurred, it is passed,
along with the corresponding load enable, to the SIG to set
the bit in the status register. If the flag condition changes, then
the clear for the corresponding bit is passed to the SIG to clear
the flag. The TDO_SM empty and the TDI_SM full flags are
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