SCANSTA101SM/NOPB National Semiconductor, SCANSTA101SM/NOPB Datasheet - Page 13

• Manufacturer Part Number: SCANSTA101SM/NOPB
• Description: IC TEST MASTER LOW-VOLT 49FBGA
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM/NOPB

• Applications: Testing Equipment
• Interface: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 49-FBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *SCANSTA101SM; *SCANSTA101SM/NOPB; SCANSTA101SM

shown in
shown in
Before the start of a vector processing the TMS_SM shifter is
loaded with the least significant 16 bits of the macro structure.
Based on the pre-shift TCK_SM count, the TMS_SM shifter
will skip (7 - pre-shift count) least significant bits. e.g., if the
pre-shift count is 4, the least significant 3 bits of the TMS_SM
shifter will not be used to drive TMS_SM during pre-shift.
Similarly, if the post-shift is less than 7 then, during post shift
only the number of bits equal to the post-shift count following
the macro structure bit 8 will be used to drive TMS_SM.
Figure
Figure
4.
3, and the TDI_SM shifter block diagram is
FIGURE 2. TMS_SM Shifter
FIGURE 3. TDO_SM Shifter
FIGURE 4. TDI_SM Shifter
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The SCANSTA101 memory is organized in big endian format.
A memory write is accomplished by two consecutive writes to
the same location. When embedded software loads the
TDO_SM memory, the least significant 16 bits are written first
and then the most significant 16 bits. Therefore, when the
Sequencer or a Vector is initialized the SSIC can directly fetch
and load the long word to the TDO_SM shifter without any
modification.
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