PDI1394P23BD ST-Ericsson Inc, PDI1394P23BD Datasheet
PDI1394P23BD
Specifications of PDI1394P23BD
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PDI1394P23BD Summary of contents
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PDI1394P23 2-port/1-port 400 Mbps physical layer interface Preliminary data Supersedes data of 2001 Jul 18 Philips Semiconductors INTEGRATED CIRCUITS 2001 Sep 06 ...
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... The PDI1394P23 is designed to interface with a Link Layer Controller (LLC), such as the PDI1394L40, or PDI1394L41. ORDER CODE 0 to +70 °C PDI1394P23BD 0 to +70 °C PDI1394P23EC 2 Preliminary data PDI1394P23 PKG ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 4.0 PIN AND BALL CONFIGURATION 4.1 LQFP CONFIGURATION 64 LREQ 1 SYSCLK 2 CNA 3 CTL0 4 CTL1 ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 4.2 LFBGA CONFIGURATION BOTTOM (BALL) VIEW Ball Signal Ball A1 AGND C1 A2 TPBIAS1 C2 A3 TPA1– AGND C5 A6 TPBIAS0 C6 A7 TPB0– AGND ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 5.0 PIN DESCRIPTION Name Pin Type LQFP Pin Numbers Numbers AGND Supply 32, 33, 39, 48, 49 Supply 30, 31, DD 42, 51, 52 BRIDGE CMOS 28 C/LKON CMOS 5V ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface Name Pin Type LQFP Pin Numbers Numbers CTL0, CMOS 5V tol 4 CTL1 5 D0–D7 CMOS 5V tol 10, 11, 12, 13 DGND Supply 17, 18, 63, 64 ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface Name Pin Type LQFP Pin Numbers Numbers PLLGND Supply 57, 58 PLLV Supply Bias RESET CMOS 5V tol 53 SYSCLK CMOS 2 TEST0 CMOS 29 TPA0+, ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 6.0 BLOCK DIAGRAM LPS /ISO C/LKON SYSCLK LREQ CTL0 LINK CTL1 INTERFACE D0 I PC0 PC1 PC2 CNA R0 R1 TPBIAS0 TPBIAS1 TWOPORT PD /RESET ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface data bits are split into two-, four- or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The LPS input is considered inactive if it remains low for more than µ 2.6 s and is considered active otherwise. When the PDI1394P23 detects that LPS is inactive, it will place ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 9.0 RECOMMENDED OPERATING CONDITIONS SYMBOL SYMBOL PARAMETER PARAMETER Supply voltage ly voltage DD DD High-level input voltage, LREQ CTL0, CTL1, D0-D7 V High-level input voltage, C/LKON IH ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 10.0 CABLE DRIVER SYMBOL SYMBOL PARAMETER PARAMETER V Differential output voltage OD I Driver Difference current, TPA+, TPA–, TPB+, TPB– O(diff) Common mode speed signaling output current, TPB ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 12.0 OTHER DEVICE I/O SYMBOL PARAMETER I Supply current DD I Supply current in power down mode DD–PD V Cable power status threshold voltage High-level output voltage, pins ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 13.0 THERMAL CHARACTERISTICS SYMBOL SYMBOL PARAMETER PARAMETER RΘjA Junction-to-free-air thermal resistance 14.0 AC CHARACTERISTICS SYMBOL PARAMETER Transmit jitter Transmit skew t TPA, TPB differential output voltage rise time r t TPA, TPB ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 16.0 INTERNAL REGISTER CONFIGURATION There are 16 accessible internal registers in the PDI1394P23. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface FIELD SIZE TYPE LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. The logical AND of this bit and ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions FIELD SIZE TYPE Link_Speed 2 Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows: This ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 17.0 APPLICATION INFORMATION PDI1394P23 CABLE PORT The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended. Figure 4. Twisted pair ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface PHY V 13 kΩ 3.3 nF SQUARE WAVE SIGNAL 9.1 kΩ Figure 8. Isolated circuit connection for LPS 2001 Sep 06 DD LINK LAYER CHIP LPS CONTENDER/ LINKON SV01807 LINK LAYER CHIP ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 17.1 External Component Connections REFER TO SECTION 17 LREQ 2 SYSCLK CNA OUT 3 CNA 4 CTL0 5 CTL1 ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 17.2 RESET and Power Down Forcing the RESET pin low resets the internal logic to the Reset Start state and deactivates SYSCLK. Returning the RESET pin high causes a Bus Reset condition ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface During bus initialization following a bus-reset, each PHY transmits a self-ID packet that indicates, among other information, the speed capability of the PHY. The bus manager (if one exists) may build a ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface NOTE: The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY’s Phase Lock Loop, and minimizing any emissions from ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 18.0 PRINCIPLES OF OPERATION The PDI1394P23 is designed to operate with an LLC such as the Philips Semiconductors PDI1394L21, PDI1394L40, or PDI1394L41. The following paragraphs describe the operation of the PHY-LLC interface. ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface LR0 LR1 18.1 LLC service request To request access to the bus, to read or write a PHY register control arbitration acceleration, the LLC sends a serial bit stream on ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 16. Table 16. Write Register Request BIT(S) NAME DESCRIPTION 0 Start Bit Indicates ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 18.4 Transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The sequence of events for a cancelled/null packet transmission is as follows: • Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface Table 20. LPS Timing Parameters PARAMETER T LPS low time (when pulsed) (see Note 1) LPSL T LPS high time (when pulsed) (see Note 1) LPSH LPS duty cycle (when pulsed) (see ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The sequence of events for resetting the PHY-LLC interface when the differentiated mode of operation (ISO terminal is low follows: 1. Normal operation. Interface is operating normally, ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The sequence of events for resetting the PHY-LLC interface when the nondifferentiated mode of operation (ISO terminal is high follows: 1. Normal operation. Interface is operating normally, ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The sequence of events for disabling the PHY-LLC interface when the differentiated mode of operation (ISO terminal is low follows: 1. Normal operation. Interface is operating normally, ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The sequence of events for disabling the PHY-LLC interface when the non-differentiated mode of operation (ISO terminal is high follows: 1. Normal operation. Interface is operating normally, ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated mode of operation (ISO terminal is low follows: 1. LPS reasserted. After the ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface 19.0 POWER-CLASS PROGRAMMING The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. Descriptions of the various ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 2001 Sep 06 40 Preliminary data PDI1394P23 SOT314-2 ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 1.05 mm 2001 Sep 06 41 Preliminary data PDI1394P23 SOT534-1 ...
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Philips Semiconductors 2-port/1-port 400 Mbps physical layer interface Data sheet status Product Definitions [1] Data sheet status [2] status Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to ...