N25Q128A11BSF40F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11BSF40F Datasheet - Page 47
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N25Q128A11BSF40F
Manufacturer Part Number
N25Q128A11BSF40F
Description
IC SRL FLASH 128MB NMX 16-SOIC
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11BSF40F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.295", 7.50mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11BSF40F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11BSF40F
Manufacturer:
MICRON
Quantity:
1 200
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6.5.7
The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is as soon as the
Program/Erase Suspend command (PES) has been issued, therefore the device may still
complete the operation before entering the Suspend Mode.
The Program Suspend Status should be considered valid when the P/E Controller bit is high
(FSR<7>=1).
When a Program/Erase Resume command (PER) is issued the Program Suspend Status bit
returns Low (FSR<2>=0)
Protection Status bit
The bit 1 of the Flag Status Register represents the Protection Status bit. It indicates that an
Erase or Program operation has tried to modify the contents of a protected array sector, or
that a modify operation has tried to access to a locked OTP space. The Protection Status bit
is related to all possible protection violations as follows:
Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag
Status Register command (CLFSR). If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
The sector is protected by Software Protection Mode 1 (SPM1) Lock registers,
The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits
(standard SPI Status Register),
An attempt to program OTP when locked,
A Write Status Register command (WRSR) on STD SPI Status Register when locked by
the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware Protection
Mode).
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