MT41J512M4HX-187E:D Micron Technology Inc, MT41J512M4HX-187E:D Datasheet - Page 117

• Manufacturer Part Number: MT41J512M4HX-187E:D
• Description: IC DDR3 SDRAM 2GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J512M4HX-187E:D

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (512M x 4)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

On-Die Termination
WRITE LEVELING
POSTED CAS ADDITIVE Latency (AL)
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
ODT resistance R
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple R
and RZQ is 240Ω.
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. R
initialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT enabled (R
replaces R
The actual effective termination, R
nonlinearity of the termination. For R
Termination (ODT)” on page 161).
The ODT feature is designed to improve signal integrity of the memory channel by
enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all
devices. The ODT input control pin is used to determine when R
on) and off (ODTL off ), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in “On-Die Termination (ODT)” on page 161.
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 53 on
page 115. Write leveling is used (during initialization) to deskew the DQS strobe to clock
offset as a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM
memory modules adopted fly-by topology for the commands, addresses, control signals,
and clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. However,
fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at
each DRAM on the DIMM. Controllers will have a difficult time maintaining
t
fly-by topology-based modules. Write leveling timing and detailed operation informa-
tion is provided in “Write Leveling” on page 103.
AL is supported to make the command and data bus efficient for sustainable band-
widths in DDR3 SDRAM. MR1[4, 3] define the value of AL as shown in Figure 54 on
page 118. MR1[4, 3] enable the user to program the DDR3 SDRAM with an AL = 0, CL - 1,
or CL - 2.
With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank prior to
ACTIVATE to READ or WRITE + AL ≥
t
t
it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by
the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of
CAS WRITE latency and AL, WL = AL + CWL (see “Mode Register 2 (MR2)” on page 118).
Examples of READ and WRITE latencies are shown in Figure 54 on page 118 and
Figure 56 on page 119.
DSS, and
RCD (MIN) = CL, a typical application using this feature sets AL = CL - 1
RCD (MIN) - 1
t
TT
DSH specifications without supporting write leveling in systems which use
_
NOM
t
CK. The READ or WRITE command is held for the time of the AL before
TT
with R
_
TT
NOM
termination values based on RZQ/n where n can be 2, 4, 6, 8, or 12
TT
is defined by MR1[9, 6, 2] (see Figure 53 on page 115). The R
TT
_
WR
_
117
NOM
.
termination is allowed any time after the DRAM is
TT
t
_
RCD (MIN) must be satisfied. Assuming
TT
EFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
_
EFF
, may be different from the R
values and calculations (see “On-Die
2Gb: x4, x8, x16 DDR3 SDRAM
t
RCD (MIN). The only restriction is
©2006 Micron Technology, Inc. All rights reserved.
TT
TT
is turned on (ODTL
_
WR
TT
) temporarily
t
targeted due to
CK =
Operations
t
DQSS,
TT