MT41J512M4HX-125:D Micron Technology Inc, MT41J512M4HX-125:D Datasheet - Page 165

• Manufacturer Part Number: MT41J512M4HX-125:D
• Description: IC DDR3 SDRAM 2GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J512M4HX-125:D

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (512M x 4)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Figure 109: Dynamic ODT: Without WRITE Command
DQS, DQS#
Command
Address
ODT
CK#
DQ
CK
R
TT
NOP
T0
DQS, DQS#
Command
Address
NOP
T1
Notes:
Notes:
ODT
CK#
DQ
R
CK
TT
Valid
NOP
T0
T2
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
1. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered
ODTL on
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
LOW at T5 is also legal.
ODTH4
NOP
T3
Valid
T1
WRS4
Valid
T4
Valid
T2
t AON (MIN)
t AON (MAX)
ODTL on
TT
NOP
t AON (MIN)
T5
t AON (MAX)
_
ODTL
NOM
ODTH4
Valid
R
T3
TT
CNW
_
ODTH4
NOM
is enabled and R
NOP
T6
WL
Valid
T4
NOP
T7
TT
ODTL
_
NOM
CWN
t ADC (MIN)
t ADC (MAX)
4
NOP
Valid
T8
and R
TT
T5
_
WR
TT
is either enabled or disabled.
NOP
_
T9
DI
n
WR
Valid
R
T6
TT
n + 1
_
DI
are enabled.
WR
NOP
T10
n + 2
DI
Valid
n + 3
T7
DI
R
NOP
T11
TT
_
NOM
Valid
t ADC (MIN)
T8
t ADC (MAX)
NOP
T12
ODTL off
t AOF (MIN)
Valid
T13
NOP
T9
t AOF (MAX)
Transitioning
R
TT
NOP
T14
_
NOM
Valid
T10
ODTL off
NOP
Transitioning
T15
Don’t Care
Valid
T11
NOP
T16
Don’t Care
t AOF (MIN)
t AOF (MAX)
NOP
T17