N25Q128A11BF840F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11BF840F Datasheet - Page 103
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N25Q128A11BF840F
Manufacturer Part Number
N25Q128A11BF840F
Description
IC SRL FLASH 128MB NMX 8-VDFPN
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11BF840F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VDFPN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11BF840F
- Current page: 103 of 185
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status register (WRSR) instruction is not executed once the hardware protected mode
(HPM) is entered.
Figure 31. Write Status Register instruction sequence
The protection features of the device are summarized in Table 8.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two
cases need to be considered, depending on the state of Write Protect (W/VPP):
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered in either of the following ways:
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP3, BP2, BP1, BP0) bits of the Status Register, can be used.
S
C
DQ0
DQ1
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction (attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP3, BP2, BP1, BP0) bits of the
Status Register, are also hardware protected against data modification.
setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
0
1
High Impedance
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
register in
4
Status
3
2
1
0
AI13735
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