DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 24
![IC MAPPER ETHERNET 100CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS33ZH11+
Manufacturer Part Number
DS33ZH11+
Description
IC MAPPER ETHERNET 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33ZH11+
Applications
Data Transport
Interface
Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
100-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
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SDATA[28]
SDATA[29]
SDATA[30]
SDATA[31]
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDA[0]
SDA[1]
SDA[2]
SDA[3]
SDA[4]
SDA[5]
NAME
AFCS
DS33Z11
CSBGA
PIN #
M12
M11
(169)
C10
H11
N13
N11
N12
H13
H12
G12
G11
N10
K13
F11
K11
L13
J13
J12
L10
L11
M1
M2
M3
N1
N2
N4
N3
H3
N9
L2
K1
K2
L1
L4
J3
J1
J2
L7
L8
DS33ZH1
BGA(100)
PIN #
H1
G2
C3
D3
C2
G1
D1
D2
G7
H7
H8
H9
C7
G9
G8
G6
C6
H6
C4
H4
F2
K1
K2
E2
F1
E1
K6
K8
K7
K9
K5
F9
J1
J2
J7
J8
J9
J5
—
1
SDRAM CONTROLLER
O
TYPE
IOZ
I
24 of 172
Automatic Flow Control (Hardware Mode): When in
Hardware Mode, set high to enable automatic flow control
pause and backpressure application. In the software
mode this pin has no effect and the rate selection is
controlled by the SU.GCR register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to V
SDRAM Data Bus (Bits 0 through 31): The 32 pins of
the SDRAM data bus are inputs for read operations and
outputs for write operations. At all other times, these pins
are high-impedance.
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
SDRAM Address Bus 0 through 11: The 12 pins of the
SDRAM address bus output the row address first, followed
by the column address. The row address is determined by
SDA0 to SDA11 at the rising edge of clock. Column
address is determined by SDA0-SDA9 and SDA11 at the
rising edge of the clock. SDA10 is used as an auto-
precharge signal.
Note: All SDRAM operations are controlled entirely by the
FUNCTION
DD
.
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