DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 81
![IC MAPPER ETHERNET 100CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS33ZH11+
Manufacturer Part Number
DS33ZH11+
Description
IC MAPPER ETHERNET 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33ZH11+
Applications
Data Transport
Interface
Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
100-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit 3: Wrap Type (WT) This bit is used to configure the wrap mode.
Bits 0- 2: Burst Length 0 through 2 (BL0 – BL2) These bits are used to determine the Burst Length.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
Register Description:
Register Address:
Bits 0 - 2: CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency
Note: Only CAS Latency of 2 or 3 is allowed
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
Register Description:
Register Address:
Bit 0: SDRAM Mode Write (SDMW) Setting this bit to 1 will write the current values of the mode control and
refresh time control registers to the SDRAM. The user must clear this bit and set it again for subsequent write
operations.
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
7
0
7
0
-
-
7
0
-
0 = Sequential
1 = Interleave
6
0
6
0
-
-
6
0
-
GL.SDMODE1
Global SDRAM Mode Register 1
3Ah
GL.SDMODE2
Global SDRAM Mode Register 2
3Bh
Global SDRAM Mode Register Write Status
3Ch
GL.SDMODEWS
5
0
5
0
-
-
5
0
-
81 of 172
4
0
4
0
-
-
4
0
-
WT
3
0
3
0
-
3
0
-
LTMOD2
BL2
0
0
2
2
2
0
-
LTMOD1
BL1
1
1
1
1
1
0
-
LTMOD0
SDMW
BL0
0
1
0
0
0
0
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