DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 9
![IC MAPPER ETHERNET 100CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS33ZH11+
Manufacturer Part Number
DS33ZH11+
Description
IC MAPPER ETHERNET 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33ZH11+
Applications
Data Transport
Interface
Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
100-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.6 SDRAM Interface
2.7 MAC Interface
2.8 Microprocessor Interface
2.9 Serial SPI Interface—Master Mode Only
2.10 Default Configurations
2.11 Test and Diagnostics
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Interface for 128 Mb, 32-bit wide SDRAM
SDRAM Interface speed up to 100 MHz
Auto refresh timing
Automatic precharge
Master clock provided to the SDRAM
No external components required for SDRAM connectivity
MAC port with standard MII (less TX_ER) or RMII
10 Mbps and 100 Mbps Data rates
Configurable DTE or DCE modes
Facilitates auto-negotiation by host microprocessor
Programmable half and full-duplex modes
Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
Programmable Maximum MAC frame size up to 2016 bytes
Minimum MAC frame size: 64 bytes
Discards frames greater than Programmed Maximum MAC frame size and Runt, non-octet bounded,
or bad-FCS frames upon reception
Configurable for promiscuous broadcast-discard mode.
Programmable threshold for SDRAM queues to initiate flow control and status indication
MAC loopback support for transmit data looped to Receive Data at the MII/RMII interface
8-bit data bus
Nonmultiplexed Intel and Motorola timing modes
Internal software reset and external hardware reset-input pin
Global interrupt output pin
Provides chip select and clock for external EEPROM
Operation up to 8.33 MHz
4-signal interface
Default Hardware Configuration for operation without an external microprocessor
Hardware modes set for easy connection to T1/T3 E1/E3 WAN systems
Hardware pins provide some flexibility for configuration
IEEE 1149.1 support
Programmable on-chip BERT
Patterns include pseudorandom QRSS, Daly, and user-defined repetitive patterns
Loopbacks (remote, local, analog, and per-channel loopback)
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