MT18LSDT6472Y-133D2 Micron Technology Inc, MT18LSDT6472Y-133D2 Datasheet - Page 6

• Manufacturer Part Number: MT18LSDT6472Y-133D2
• Description: MODULE SDRAM 512MB 168RDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18LSDT6472Y-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Features: -
• Package / Case: 168-RDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Description
PLL and Register Operation
PDF: 09005aef809b161a/Source: 09005aef809b15eb
SD18C32_64_128x72.fm - Rev. E 1/08 EN
The MT18LSDT3272, MT18LSDT6472, and MT18LSDT12872 are high-speed, CMOS
dynamic random access 256MB, 512MB, and 1GB memory modules organized in a x72
ECC configuration. SDRAM modules use 4-bank SDRAM devices with a synchronous
interface (all signals are registered on the positive edge of clock signal CK).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A11 select the device row for the 256MB module; A0–A12
select the device row for the 512MB and 1GB modules). The address bits registered coin-
cident with the READ or WRITE command are used to select the starting device column
location for the burst access.
SDRAM modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed device row precharge that is initiated at the end of the
burst sequence.
SDRAM modules use an internal pipelined architecture. Precharging one device bank
while accessing one of the other three device banks will hide the PRECHARGE cycles and
provide seamless, high-speed, random-access operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving power-down mode. All inputs and
outputs are LVTTL compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic device
column-address generation, the ability to interleave between device banks to hide
precharge time, and the capability to randomly change device column addresses on
each clock cycle during a burst access. For more information regarding SDRAM opera-
tion, refer to the 128Mb, 256Mb, and 512Mb SDRAM component data sheets.
These SDRAM modules either can be operated in registered mode (REGE pin HIGH),
where the control/address input signals are latched in the register on one rising clock
edge and sent to the SDRAM devices on the following rising clock edge (data access is
delayed by one clock), or in buffered mode (REGE pin LOW), where the input signals
pass through the register/buffer to the SDRAM devices on the same clock. A phase-lock
loop (PLL) on the modules is used to redrive the clock signals to the SDRAM devices to
minimize system clock loading (CK0 is connected to the PLL, and CK1, CK2, and CK3 are
terminated).
256MB, 512MB, 1GB (x72, ECC, SR): 168-Pin SDRAM RDIMM
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2003 Micron Technology, Inc. All rights reserved