ISP1562BEGE ST-Ericsson Inc, ISP1562BEGE Datasheet - Page 23

• Manufacturer Part Number: ISP1562BEGE
• Description: IC USB PCI HOST CTRLR 100-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1562BEGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3157; ISP1562BE

NXP Semiconductors
Table 23.
Legend: * reset value
[1]
Table 24.
Legend: * reset value
[1]
ISP1562_2
Product data sheet
Bit
7 to 0
Bit
7 to 0
X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.
X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.
Symbol
MIN_GNT[7:0] R
Symbol
MAX_LAT[7:0]
MIN_GNT - Minimum Grant register (address 3Eh) bit description
MAX_LAT - Maximum Latency register (address 3Fh) bit description
8.2.1.16 MIN_GNT and MAX_LAT registers
8.2.1.17 TRDY _TIMEOUT - TRDY Timeout register
8.2.1.18 RETRY__TIMEOUT - Retry Timeout register
The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to
specify the desired settings of the device for latency timer values. For both registers, the
value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no
major requirements for setting latency timers.
The MIN_GNT register bit description is given in
The MAX_LAT register bit description is given in
This is a read and write register at address 40h. The default and recommended value is
00h, TRDY time-out disabled. This value can, however, be modified. It is an
implementation-specific register, and not a standard PCI configuration register.
The TRDY timer is 13 bits: the lower 5 bits are fixed as logic 0, and the upper 8 bits are
determined by the TRDY Timeout register value. The time-out is calculated by multiplying
the 13-bit timer with the PCICLK cycle time.
This register determines the maximum TRDY delay, without asserting the UE
(Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register
value, then the UE bit will be set.
The default value of this read and write register is 80h, and is located at address 41h. This
value can, however, be modified. Programming this register as 00h means that retry
time-out is disabled. This is an implementation-specific register, and not a standard PCI
configuration register.
The time-out is determined by multiplying the register value with the PCICLK cycle time.
This register determines the maximum number of PCI retires before the UE bit is set. If the
number of retries is longer than the delay determined by this register value, then the UE
bit will be set.
Access
Access
R
Value
X*
Value
X*
[1]
[1]
Description
MIN_GNT: It is used to specify how long a burst period the device needs,
assuming a clock rate of 33 MHz.
Description
MAX_LAT: It is used to specify how often the device needs to gain access
to the PCI bus.
Rev. 02 — 1 March 2007
Table
Table
24.
23.
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1562
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