ISP1563BMUM ST-Ericsson Inc, ISP1563BMUM Datasheet - Page 102

• Manufacturer Part Number: ISP1563BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-T; ISP1563BM-T

Philips Semiconductors
27. Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10: REVID - Revision ID register (address 08h)
Table 11: Class Code register (address 09h) bit
Table 12: Class Code register (address 09h) bit
Table 13: CLS - CacheLine Size register (address 0Ch)
Table 14: LT - Latency Timer register (address 0Dh)
Table 15: Header Type register (address 0Eh) bit
Table 16: Header Type register (address 0Eh) bit
Table 17: BAR 0 - Base Address register 0 (address 10h)
Table 18: SVID - Subsystem Vendor ID register
Table 19: SID - Subsystem ID register (address 2Eh)
Table 20: CP - Capabilities Pointer register (address 34h)
Table 21: IL - Interrupt Line register (address 3Ch) bit
Table 22: IP - Interrupt Pin register (address 3Dh) bit
Table 23: Min_Gnt - Minimum Grant register
Table 24: Max_Lat - Maximum Latency register
Table 25: EHCI-specific PCI registers . . . . . . . . . . . . . . .25
Table 26: SBRN - Serial Bus Release Number register
Table 27: FLADJ - Frame Length Adjustment register
9397 750 14224
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
PCI configuration space registers of OHCI1,
OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .16
VID - Vendor ID register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DID - Device ID register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Command register (address 04h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Command register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Status register (address 06h) bit allocation . . .19
Status register (address 06h) bit description . .19
bit description . . . . . . . . . . . . . . . . . . . . . . . . .20
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
(address 2Ch) bit description . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .24
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(address 3Eh) bit description . . . . . . . . . . . . . .24
(address 3Fh) bit description . . . . . . . . . . . . . .25
(address 60h) bit description . . . . . . . . . . . . . .26
Rev. 01 — 14 July 2005
Table 28: FLADJ - Frame Length Adjustment register
Table 29: PORTWAKECAP - Port Wake Capability
Table 30: Power Management registers . . . . . . . . . . . . . 27
Table 31: Cap_ID - Capability Identifier register bit
Table 32: Next_Item_Ptr - Next Item Pointer register bit
Table 33: PMC - Power Management Capabilities
Table 34: PMC - Power Management Capabilities
Table 35: PMCSR - Power Management Control/Status
Table 36: PMCSR - Power Management Control/Status
Table 37: PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 38: PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 39: PCI bus power and clock control . . . . . . . . . . . 32
Table 40: Data register bit description . . . . . . . . . . . . . . 32
Table 41: USB Host Controller registers . . . . . . . . . . . . . 36
Table 42: HcRevision - Host Controller Revision register
Table 43: HcRevision - Host Controller Revision register
Table 44: HcControl - Host Controller Control register
Table 45: HcControl - Host Controller Control register
Table 46: HcCommandStatus - Host Controller
Table 47: HcCommandStatus - Host Controller
Table 48: HcInterruptStatus - Host Controller
Table 49: HcInterruptStatus - Host Controller
Table 50: HcInterruptEnable - Host Controller
Table 51: HcInterruptEnable - Host Controller
Table 52: HcInterruptDisable - Host Controller
Table 53: HcInterruptDisable - Host Controller
(address 61h) bit allocation . . . . . . . . . . . . . . . 26
(address 61h) bit description . . . . . . . . . . . . . . 26
register (address 62h) bit description . . . . . . . 27
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
register bit allocation . . . . . . . . . . . . . . . . . . . . 28
register bit description . . . . . . . . . . . . . . . . . . . 28
register bit allocation . . . . . . . . . . . . . . . . . . . . 30
register bit description . . . . . . . . . . . . . . . . . . . 30
Support Extensions register bit allocation . . . . 31
Support Extensions register bit description . . . 32
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 38
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 39
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40
Command Status register bit allocation . . . . . 42
Command Status register bit description . . . . 42
Interrupt Status register bit allocation . . . . . . . 43
Interrupt Status register bit description . . . . . . 44
Interrupt Enable register bit allocation . . . . . . . 45
Interrupt Enable register bit description . . . . . 45
Interrupt Disable register bit allocation . . . . . . 46
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
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