DP83266VF National Semiconductor, DP83266VF Datasheet
DP83266VF
Specifications of DP83266VF
Related parts for DP83266VF
DP83266VF Summary of contents
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... Y Full duplex operation with through parity Y Supports JTAG boundary scan Y Real-time Void stripping indicator for bridges Y Block Diagram FIGURE 1-1 FDDI Chip Set Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation BMAC TM BSI-2 TM MACSI TM and PLAYER TM are trademarks of National Semiconductor Corporation ...
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FDDI CHIP SET OVERVIEW 2 0 GENERAL FEATURES 2 1 FDDI MAC Support 2 2 MAC Addressing Support 2 3 MAC Bridging Support 2 4 MAC Service Class Support 2 5 Diagnostic Counters 2 6 Management Services 2 ...
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... FDDI Chip Set Overview National Semiconductor’s FDDI chip set is shown in Figure 1-1 For more information about the PLAYER consult the appropriate datasheet and application notes DP83256 56-AP 57 PLAYER Device Physical Layer Controller The PLAYER device implements the Physical Layer ...
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General Features The DP83266 MACSI device is a highly integrated FDDI controller Together with the DP83256 57 PLAYER vice it forms a full-featured high performance FDDI chip set useful for designing end station attachments concentrators bridges routers and ...
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General Features (Continued) These paths allow error isolation at the device level The MACSI device also supports through parity Even when parity is not used by the system parity support can be pro- vided across the PHY Interface ...
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General Features (Continued) In addition to the 4 6 kByte data FIFOs both the transmit and receive data paths contain Burst FIFO Blocks each of which are organized as two banks of eight 32-bit words 2 21 FRAME-PER-PAGE-PER-CHANNEL ...
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Architectural Description 3 1 INTERFACES PHY Interface The PHY Interface is a synchronous interface that provides a byte stream to the PLAYER device (the PHY Request a byte stream PHY Request) and receives a byte ...
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Architectural Description During frame transmission the Transmitter performs the fol- lowing functions Captures a token to gain the right to transmit Transmits one or more frames Generates the Frame Check Sequence and appends it at the end of ...
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Architectural Description Confirmation Messages (CNFs) are created by the MACSI device to record the result of a Request operation Pool Space Descriptors (PSPs) describe the location and size of a region of memory space available for writing Input ...
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Architectural Description FIGURE 3-3 MACSI Device Data Structures (Continued) Request Data Structures Indicate Data Structures 11705 – 11705 – 5 ...
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Architectural Description FIGURE 3-4 Service Engine BIU Internal Block Diagram Upon receiving the data the Indicate Block performs the following functions Decodes the Frame Control field to determine frame type Sorts received frames onto Channels according to the ...
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Architectural Description (Continued) Each Channel will only process one object type at a time The BIU arbitrates between the Channels and issues a Bus Request when any Channel requests service The priority of Channel bus requests is as ...
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FDDI MAC Facilities (Continued Frame Fields Start of Frame Sequence (SFS) The Start of Frame Sequence consists of the Preamble (PA) followed by the Starting Delimiter (SD) The Preamble is a sequence of zero or ...
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FDDI MAC Facilities (Continued) On the receive side the incoming SA is compared with ei- ther MSA or MLA If a match occurs between the incoming SA and this station’s MLA or MSA the MFlag is set This ...
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FDDI MAC Facilities (Continued) Frames Generated Externally The Ring Engine transmits frames passed to it from the Sys- tem Interface The data portion of the frame is created by the System Interface The data portion begins with the ...
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FDDI MAC Facilities (Continued) Type Enable Size Void ESA Short Void not ESA Long My Void ESA Short My Void not ESA Long Type Enable Size My Claim not ELA Short My Claim ELA Long Type Enable Size ...
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FDDI MAC Facilities (Continued Frames Not Copied Count (FNCT) The Frames Not Copied Count is specified in the FDDI MAC standard and is the count of frames intended for this station that were not successfully ...
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FDDI MAC Facilities (Continued) Each time the token arrives a station is permitted to trans- mit one or more frames in accordance with its synchronous bandwidth allocation regardless of the status of the token (late or early Restricted ...
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Functional Description is not received within TTRT (the token is late) the event is recorded by setting the Late Flag If the token is not re- ceived within twice TTRT (TRT expires and Late Flag is set) there ...
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Functional Description (Ring Engine) A Service Opportunity begins when the criteria presented to the Ring Engine are met This criteria contains the request- ed service class (sync async async priority immediate) and the type of token to capture ...
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Functional Description (Ring Engine) transmission is aborted due to an external error (and Option IRPT is not set) a Void frame is transmitted to reset the TVX timers in all stations in the ring When a frame is ...
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Functional Description (Ring Engine) If any frame of a service opportunity requests this option then all frames on that service opportunity will be stripped using this method Void Stripping is invoked upon the asser- tion of the STRIP ...
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Functional Description (Ring Engine) RQRCLS Name 0000 None 0001 Apri 1 THSH1 0010 Reserved Reserved 0011 Reserved Reserved 0100 Sync 0101 Imm Immediate 0110 ImmN Immediate 0111 ImmR Immediate 1000 Async 1001 Rbeg Restricted 1010 Rend Restricted 1011 ...
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Functional Description (Ring Engine) The Ending Delimiter followed by the Frame Status Indica- tors should begin and end on byte boundaries Control Indi- cators are repeated until the first non symbol is received The ...
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Functional Description (Ring Engine) Additionally only the station that sets the A Indicator is per- mitted to set the C Indicator on such frames In this way the station that sends out the NSA frame can determine if ...
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Functional Description (Ring Engine Handling Reserved MAC Frames A Reserved MAC frame is any MAC frame aside from Bea- con and Claim frames Tokens are not considered MAC frames even though their Format bit (FC ...
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Functional Description (Ring Engine) (Continued) On the PHY Request interface parity is generated for inter- nally sourced fields (such as the SA or FCS on frames when not using SA or FCS transparency and internally generated Beacon Claim ...
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Functional Description (Service Engine) With High-priority Low-priority sorting high-priority asyn- chronous frames are sorted onto Indicate Channel 1 and low-priority asynchronous frames are sorted onto Indicate Channel 2 The most-significant bit of the three-bit priority field within the ...
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Functional Description (Service Engine) The MACSI device provides the ability to group incoming frames and then generate interrupts (via attentions) at group boundaries To group incoming frames the MACSI device defines status breakpoints which identify the end of ...
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Functional Description (Service Engine) Request status is generated as a single confirmation object (single- or multi-part) per Request object with each confir- mation object consisting of one or more CNF Descriptors The type of confirmation is specified by ...
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Functional Description (Service Engine) FIGURE 6-2 MACSI Device External Matching Interface Timing Note that this design allows ECIP positive or nega- tive pulse To confirm frames in this mode (typically with Source Address Transparency enabled) ...
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Functional Description (Service Engine) enabled Therefore for applications which do not use exter- nal address matching ECIP should be tied low Note also that if ECIP remains asserted to the point where the incom- ing frame data completely ...
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Functional Description (Service Engine) The MACSI device has a mode for controlling the ABus Ad- dress Strobe (AB AS) In the default mode driven active during the address cycle and remains low throughout the access ...
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Functional Description (Service Engine) current transaction Note that Bus Request is guaranteed to be de-asserted for at least two cycles when MR1 EAM is enabled requirement of the SBus specification that Bus Request be de-asserted ...
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Functional Description (Service Engine) Master States The Ti state exists when no bus activity is required The BIU does not drive any of the bus signals when this state (all are released) If the BIU ...
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Functional Description (Service Engine) Single Read Tbr MACSI device asserts indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to Tpa within the next three clocks Tpa MACSI ...
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Functional Description (Service Engine) FIGURE 6-6 ABus Burst Read Physical Addressing 16 Bytes Burst Read Tbr MACSI device asserts indicate it wishes to perform a transfer Host asserts AB BG The MACSI ...
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Functional Description (Service Engine) FIGURE 6-7 ABus Burst Write Physical Addressing 16 Bytes Virtual Addressing Bus Transactions Single Read Tbr MACSI device asserts indicate it wishes to perform a ...
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Functional Description (Service Engine) Tmmu Host MMU performs an address translation during this clock Tpa Host MMU drives AB AD with the address Td MACSI device negates AB AS asserts AB DEN drives AB AD with the write ...
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Functional Description (Service Engine) FIGURE 6-8 Enhanced ABus Read Timing FIGURE 6-9 Enhanced ABus Mode Write Timing (Continued 11705 – 11705 – 14 ...
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Functional Description (Service Engine) FIGURE 6-10 Enhanced ABus Mode Burst Write Timing Single Write Tbr MACSI device asserts indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to ...
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Functional Description (Service Engine) FIGURE 6-11 Enhanced ABus Mode Back-to-Back Read Timing Burst Read Tbr MACSI device asserts indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to ...
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Control Information 7 1 OVERVIEW The Control Information includes Operation Event Status and Parameter Registers that are used to manage and op- erate the MACSI Device A controller on the external Con- trol Bus gains access to read ...
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Control Information (Continued) TABLE 7-1 MACSI Memory Map (BMAC Registers) (Continued) Address Register Name 028 Internal Event Latch Register (IELR) 029 –02B Reserved 02C Exception Status Register (ESR) 02D Exception Mask Register (EMR) 02E Interrupt Condition Register (ICR) ...
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Control Information (Continued) Table 7-2 MACSI Memory Map (BSI Registers) Address Register Name 114 Indicate Attention Register (IAR) 115 Indicate Notify Register (INR) 116 Indicate Threshold Register (ITR) 117 Indicate Mode Configuration Register (IMCR) 118 Indicate Copy Configuration ...
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Control Information (Continued) TABLE 7-3 MAC Control Information Address Space Address Description Range 000–007 Operation Registers 008–02F Event Registers 030–03F Reserved 040–07F MAC Parameters 080-0BF Counters Timers 0C0-0FF Reserved Note 1 An attempt to access a currently inaccessible ...
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Control Information (Continued) Addr Name D7 D6 008 MCCMP 009–00B Reserved RES RES 00C CRS0 RFLG RS2 00D Reserved RES RES 00E CTS0 ROP TS2 00F Reserved RES RES 010 RELR0 RES DUP ADD 011 REMR0 RES DUP ...
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Control Information (Continued) Addr Name Register Contents 040 MLA0 MLA(47–40) 041 MLA1 MLA(39–32) 042 MLA2 MLA(31–24) 043 MLA3 MLA(23–16) 044 MLA4 MLA(15–8) 045 MLA5 MLA(7–0) 046 MSA0 MSA(15–8) 047 MSA1 MSA(7–0) 048 GLA0 GLA(47–40) 049 GLA1 GLA(39–32) 04A ...
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Control Information (Continued) TABLE 7-7 MAC Counters and Timer Thresholds Addr Name Register Contents 080 –086 Reserved 087 THSH1 Null(7–4) THSH1(3 – 0) 088 –092 Reserved 093 TMAX Null(7–4) TMAX(3 – 0) 094 –096 Reserved 097 TVX Null(7–4) ...
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Control Information (Continued) System Interface Registers Addr Name D7 D6 100 SIMR0 SMLB SMLQ 101 SIMR1 AB A31 AB A30 AB A29 AB A28 102 PCAR BP1 BP0 PTRW 103 MBAR Mailbox Address 27 24 104 MAR STA ...
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Control Information (Continued) Control Registers The Control Registers are used to configure and control the operation of the MACSI device The Control Registers include the following registers MAC Mode Registers (MCMR2–0) establish the major operating parameters for the ...
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Control Information (Continued) The MACSI device has two interrupts signals One provides interrupts on those events generated by the MAC state ma- chines (INT0) and the other provides interrupts on those events generated by the System Interface state ...
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Control Information (Continued RING ENGINE OPERATION REGISTERS The Operation Registers are used to control the operation of the Ring Engine The Operation Registers include the following registers MAC Mode Register (MCMR0 MCMR2) Option Register (Option) Function ...
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Control Information (Continued) Option Register (Option) The Ring Engine supports several options These options are typically static during operation but may be altered during operation This register is initialized to Zero after a master reset Access Rules Address ...
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Control Information (Continued) Bit Symbol D3 IRR Inhibit Recovery Required When bit IRR is set to One the Ring Engine does not take the transitions into the Claim state (T4) This option inhibits all the recovery required transitions ...
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Control Information (Continued) Function Register (Function) The Ring Engine performs the MAC Reset Claim Request and Beacon Request using the Function Register The Register is initialized to Zero after a master reset A function is performed by setting ...
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Control Information (Continued) MAC Mode Register 2 (MCMR2) The Mode Register 2 (MCMR2) is used to program major operating parameters for the MAC portion of the MACSI device This register should be programmed only at power-on or after ...
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Control Information (Continued) MAC Compare Register (MCCMP) The Compare Register is written with the contents of a conditional event latch register when it is read The Compare Register may also be written to directly Access Rules Address Read ...
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Control Information (Continued) Current Receiver Status Register (CRS0) The Current Receiver Status Register (CRS0) records the status of the Receiver state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is ...
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Control Information (Continued) Current Transmitter Status Register (CTS0) The Current Transmitter Status Register (CTS0) records the status of the Transmitter state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is ...
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Control Information (Continued) Ring Event Latch Register 0 (RELR0) The Ring Event Latch Register 0 (RELR0) captures conditions that occur on the Ring including the receipt of Beacon and Claim frames transitions in the Ring Operational flag and ...
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Control Information (Continued) Ring Event Mask Register 0 (REMR0) The Ring Event Mask Register 0 (REMR0) is used to mask bits in Register RELR0 If a bit in Register REMR0 is set to One the corresponding bit in ...
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Control Information (Continued) Ring Event Mask Register 1 (REMR1) Ring Event Mask Register 1 is used to mask bits in Register RELR1 If a bit in Register REMR1 is set to One the corresponding bit in Register RELR1 ...
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Control Information (Continued) Token and Timer Event Latch Register 0 (TELR0) The Token and Timer Event Latch Register 0 (TELR0) informs software of time expirations of the Token Rotation Timer (TRT) and Valid Transmission Timer (TVX) The TELR0 ...
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Control Information (Continued) Token and Timer Event Mask Register 0 (TEMR0) The Token and Timer Event Mask Register 0 (TEMR0) is used to mask bits in Register TELR0 If a bit in Register TEMR0 is set to One ...
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Control Information (Continued) Counter Increment Latch Register (CILR) The Counter Increment Latch Register (CILR) records the occurrence of any increment to the SMT Counters in the Ring Engine Each bit corresponds to a counter and is set when ...
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Control Information (Continued) Counter Increment Mask Register (CIMR) The Counter Increment Mask Register (CIMR) is used to mask bits from the Counter Increment Latch Register (CILR bit in Register CIMR is set to One the corresponding ...
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Control Information (Continued) Counter Overflow Latch Register (COLR) The Counter Overflow Latch Register (COLR) records carry events from the 20th bit of the SMT Counters in the Ring Engine Each bit in the COLR corresponds to an individual ...
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Control Information (Continued) Counter Overflow Mask Register (COMR) The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR bit in Register COMR is set to One the corresponding ...
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Control Information (Continued) Internal Event Latch Register (IELR) The Internal Event Latch Register (IELR) reports internal errors in the Ring Engine These errors include MAC Parity errors and inconsistencies in the Receiver and Transmitter state machines After an ...
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Control Information (Continued) Exception Status Register (ESR) The Exception Status Register (ESR) reports errors to the software Errors include PHY Interface Parity Errors illegal attempts to access currently inaccessible registers and writing to a conditional write location if ...
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Control Information (Continued) Exception Mask Register (EMR) The Exception Mask Register (EMR) is used to mask bits in the Exception Status Register (ESR bit in Register EMR is set to One the corresponding bit in Register ...
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Control Information (Continued) Interrupt Condition Register (ICR) The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers Interrupts are categorized into Ring Events Token and Timer Events Counter Events and Error and Exceptional Status Events If ...
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Control Information (Continued) Interrupt Mask Register (IMR) The Interrupt Mask Register (IMR) is used to mask bits in the Interrupt Condition Register (ICR bit in Register IMR and the corresponding bit in Register ICR are set ...
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Control Information (Continued MAC PARAMETERS The MAC Parameters are accessible in the Stop Mode These parameters are also accessible in the Run Mode when the following conditions are met a the MAC Transmitter is in state ...
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Control Information (Continued Group Addresses The Ring Engine supports detection of Group Addresses within programmable and fixed blocks of consecutive addresses The algorithm used by the Ring Engine first performs a comparison between the most ...
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Control Information (Continued) Fixed Group Address MAP (FGM0–FGM1) If the first 44 bits of a long DA DA(47–4) or the first 12 bits of a short DA DA(15– 4) are 1 the last 4 bits of the DA ...
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Control Information (Continued) Access Rules Address Read Write 060–06Fh Stop Mode Stop Mode Register Bits PGM10 PGM(87) PGM(86) PGM(85) PGM11 PGM(8F) PGM(8E) PGM(8D) PGM12 PGM(97) PGM(96) PGM(95) PGM13 PGM(9F) PGM(9E) PGM(9D) PGM14 PGM(A7) PGM(A6) PGM(A5) ...
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Control Information (Continued Beacon Information Transmit Beacon Type (TBT) Transmit Beacon Type 0 (TBT0) represents the Transmit Beacon Type to be transmitted in the Information field of a Beacon frame TBT1–TBT3 are not used by ...
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Control Information (Continued Asynchronous Priority Threshold (THSH1) The Ring Engine currently supports one Asynchronous Priority Threshold in addition to the default threshold at TTRT The Asynchronous Priority Threshold is used in a magnitude comparison with ...
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Control Information (Continued Maximum Token Rotation Time (TMAX) The Maximum Token Rotation Time (TMAX) denotes the maximum Target Token Rotation Time supported by this station TMAX is stored as a 4-bit value that is expanded ...
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Control Information (Continued Valid Transmission Time (TVX) The Valid Transmission Timer (TVX) is used to increase the responsiveness of the ring to errors that cause ring recovery The TVX value denotes the maximum time in ...
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Control Information (Continued) Negotiated Target Rotation Time (TNEG0–3) The Negotiated Target Rotation Time (TNEG0– 32-bit twos complement value It is the result of the Claim process TNEG is loaded either directly from the received Claim Information ...
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Control Information (Continued EVENT COUNTERS The Event Counters are used to gain access to the internal 20-bit counters used to gather statistics The following event counters are included Frame Received Counter (FRCT1–3) Error Isolated Counter (EICT1–3) ...
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Control Information (Continued) Late Count Counter (LTCT) The Late Count Counter (LTCT) is implemented differently than suggested by the FDDI MAC Standard but provides similar information The function of the Late Count Counter is divided between the Late ...
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Control Information (Continued) Frame Received Counter (FRCT) The Frame Received Counter (FRCT) is specified in the FDDI MAC Standard It is the count of all complete frames received including MAC frames Void frames and frames stripped by this ...
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Control Information (Continued) Lost Frame Counter (LFCT) The Lost Frame Counter (LFCT) is specified in the FDDI MAC Standard It is the count of all instances where a Format Error is detected in a frame or token such ...
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Control Information (Continued) Frame Not Copied Counter (FNCT) The Frame Not Copied Counter (FNCT) maintains a count of the number of frames intended for this station that were not successfully copied by this station This count can be ...
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Control Information (Continued) Token Received Counter (TKCT) The Token Received Counter (TKCT) maintains the count of valid tokens received by this station The counter can be used with the Ring Latency Counter to calculate the average network load ...
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Control Information (Continued) System Interface Mode Register 0 (SIMR0) The System Interface Mode Register 0 (SIMR0) is used to program major operating parameters for the System Interface of the MACSI device This register should be programmed only at ...
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Control Information (Continued) System Interface Mode Register1 (SIMR1) The System Interface Mode Register 1 (SIMR1) is used to program major operating parameters for the System Interface of the MACSI device This register should be programmed only at power-on ...
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Control Information (Continued) Pointer RAM Control and Address Register (PCAR) The Pointer RAM Control and Address Register (PCAR) is used to program the parameters for the PTOP (Pointer RAM Operation) service function in which data is written to ...
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Control Information (Continued) Master Attention Register (MAR) The Master Attention Register (MAR) collects enabled attentions from the State Attention Register Service Attention Register No Space Attention Register Request Attention Register and Indicate Attention Register If the Notify bit ...
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Control Information (Continued) State Attention Register (STAR) The State Attention Register (STAR) controls the state of the Indicate Request and Status Space Machines It also records parity internal logic and ABus transaction errors Each bit may be enabled ...
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Control Information (Continued) State Notify Register (STNR) The State Notify Register (STNR) is used to enable bits in the State Attention Register (STAR bit in the STNR is set to One the corresponding bit in Register ...
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Control Information (Continued) Service Attention Register (SAR) The Service Attention Register (SAR) is used to present the attentions for the service functions Each bit may be enabled by setting the corresponding bit in the State Notify Register This ...
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Control Information (Continued) Service Notify Register (SNR) The Service Notify Register (SNR) is used to enable attentions in the Service Attention Register (SAR bit in Register SNR is set to One the corresponding bit in Register ...
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Control Information (Continued) No Space Attention Register (NSAR) The No Space Attention Register (NSAR) presents the attentions generated when the CNF PSP or IDUD Queues run out of space The host may set any attention bit to cause ...
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Control Information (Continued) Bit Symbol D4 NSI0 No Status Space on ICHN0 This bit is set by the MACSI device upon a Reset or when an IDUD has been written to the next-to-last available entry in the Indicate ...
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Control Information (Continued) No Space Notify Register (NSNR) The No Space Notify Register (NSNR) is used to enable attentions in the No Space Attention Register (NSAR bit in Register NSNR is set to One the corresponding ...
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Control Information (Continued) Limit Data Register (LDR) The Limit Data Register (LDR) is used to hold the 8 least-significant Limit RAM data bits transferred in an LMOP service function (The most-significant data bit is in the Limit Address ...
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Control Information (Continued) Request Attention Register (RAR) The Request Attention Register (RAR) is used to present exception breakpoint request complete and unserviceable request attentions generated by each Request Channel Each bit may be enabled by setting the corresponding ...
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Control Information (Continued) Bit Symbol D5 EXCR0 Exception on RCHN0 This bit is set by the MACSI device when an exception occurs on RCHN0 An exception condition consists of one of the following events ABus Error Consistency Failure ...
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Control Information (Continued) Request Notify Register (RNR) The Request Notify Register (RNR) is used to enable attentions in the Request Attention Register (RAR bit in Register RNR is set to One the corresponding bit in Register ...
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Control Information (Continued) Request Channel 0 and 1 Configuration Registers 0 (R0CR0 and R1CR0) The two Request Configuration Registers 0 (R0CR0 and R1CR0) are programmed with operational parameters for each of the Request Channels Additional Request Channel parameters ...
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Control Information (Continued) Bit Symbol D5 PRE Preempt Prestage When this bit is set preemption is enabled for RCHN0 and prestaging is enabled for RCHN1 (prestaging is always enabled for RCHN0) When this bit is Zero preemption is ...
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Control Information (Continued) Request Channel 0 and 1 Expected Frame Status Registers (R0EFSR and R1EFSR) The Expected Frame Status Registers (R0EFSR and R1EFSR) define the matching criteria used for Full Confirmation of returning frames on each Request Channel ...
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Control Information (Continued) Indicate Attention Register (IAR) The Indicate Attention Register (IAR) is used to present exception and breakpoint attentions generated by each Indicate Channel An Attention bit is set by hardware when an exception or breakpoint occurs ...
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Control Information (Continued) Indicate Notify Register (INR) The Indicate Notify Register (INR) is used to enable attentions in the Indicate Attention Register (IAR bit in Register INR is set to One the corresponding bit in Register ...
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Control Information (Continued) Indicate Mode Configuration Register (IMCR) The Indicate Mode Configuration Register (IMCR) defines configuration options for all three indicate Channels including the sort mode frame filtering and status breakpoints This register may be written only when ...
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Control Information (Continued) Bit Symbol D7 –D6 SM1–0 Sort Mode These bits determine how the MACSI device sorts Indicate data onto Indicate Channels 1 and 2 SM1 SM0 0 0 Asynchronous Low ...
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Control Information (Continued) Indicate Copy Configuration Register (ICCR) The Indicate Copy Configuration Register (ICCR) is used to program the copy criteria for each of the Indicate Channels This register is not altered upon reset Access Rules Address Read ...
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Control Information (Continued) Indicate Header Length Register (IHLR) The Indicate Header Length Register (IHLR) defines the length (in words) of the frame header for use with the Header Info Sort Mode The Indicate Header Length Register must be ...
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Control Information (Continued) Address Configuration Register (ACR) This register contains bits for configuring the address swapping logic All bits in this register are set to Zero upon reset Access Rules Address Read 11Ah Always Register Bits D7 D6 ...
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Control Information (Continued) Request Channel 0 and 1 Configuration Registers 1 (R0CR1 and R1CR1) The two Request Configuration Registers 1 (R0CR1 and R1CR1) are programmed with additional operational parameters for each of the Request Channels Other Request Channel ...
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Control Information (Continued) System Interface Compare Register (SICMP) The System Interface Compare Register (SICMP) is used in comparison with a write access of a conditional write register The System Interface Compare Register is loaded on a read of ...
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Control Information (Continued POINTER RAM REGISTER DESCRIPTIONS The Pointer RAM Register set contains 32 28-bit registers Registers 23 through 31 are reserved and user access of these locations produces undefined results Pointer RAM Registers are read ...
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Control Information (Continued) Group Address 16–1F Note Bit position D2 of these Pointer RAM Locations is ...
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Control Information (Continued) Input Data Unit Descriptor (IDUD) Input Data Unit Descriptors (IDUDs) are generated on Indicate Channels to describe where the MACSI device wrote each frame part and to report status for the frame For multi-part IDUDs ...
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Control Information (Continued) Bit Symbol Word 0 (Continued) D27 –D24 FRA Frame Attributes This field gives termination and address information D25 –D24 TC Termination Condition 00 Other (e g MAC Reset token Format error 11 ...
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Control Information (Continued) NON-END FRAME STATUS 0000 Last IDUD of Queue with a Page Cross The last available location of the ICHN’s IDUD queue was written Since there was a page cross there was more data to be ...
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Control Information (Continued) REQ Descriptor (REQ) Request Descriptors (REQs) contain the part byte address and size of one or more Output Data Unit Descriptors They also contain parameters and commands to the MACSI device associated with Request operations ...
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Control Information (Continued) Bit Symbol Word 0 (Continued) D15 –D12 CNFCLS Confirmation Class (Continued) D15 R Repeat Enables repeated transmission of the first frame of the request until the request is aborted This may be used when sending ...
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Control Information (Continued) RQCLS RQCLS Value Name 0000 None 0001 Apr1 Async pri1 0010 Reserved Reserved 0011 Reserved Reserved 0100 Syn 0101 Imm 0110 ImmN 0111 ImmR 1000 Asyn 1001 Rbeg Restricted 1010 Rend Restricted 1011 Rcnt Restricted ...
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Control Information (Continued) Output Data Unit Descriptor (ODUD) An Output Data Unit Descriptor (ODUD) contains the part byte address and size of an Output Data Unit During Request operations ODUDs are fetched by the MACSI device from a ...
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Control Information (Continued) Confirmation Status Message Descriptor (CNF) A Confirmation Status Message (CNF) describes the result of a Request operation A more detailed description of the encoding of the RS bits is given in Figure 7 ...
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Control Information (Continued) Bit Symbol Word 0 (Continued) D27 –D24 FRA Frame Attributes This field is valid only for Full Confirmation D25–D24 TC Termination Condition 00 Other (e g MAC Reset token Format error 11 ...
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Control Information (Continued) Bit Symbol Word 1 D7 –D0 RES Reserved D15–D8 CS Confirmation Status D9 –D8 FT Frame Type This field reflects the type of frame that ended Full Confirmation 00 Any Other 01 Token 10 Other ...
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Control Information (Continued) INTERMEDIATE 0000 NONE Non status is written This may be used by software to identify a NULL or invalid CNF 0001 Preempted RCHN1 was preempted by RCHN0 RCHN1 will be serviced following RCHN0 0010 Part ...
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Control Information (Continued) Pool Space Descriptor (PSP) Pool Space Descriptors (PSPs) contain the address of a free space in host memory available for writing Input Data Units The count field is not used The space is assumed to ...
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Signal Descriptions The DP83266 MACSI device is packaged in a 160-pin Plastic Quad Flat Pack The signals are divided into the following interfaces Control Interface Used for microprocessor access to the Ring Engine and Service Engine PHY Interface ...
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Signal Descriptions (Continued PHY INTERFACE The PHY Interface signals transfer symbol pairs between the MACSI and PLAYER the 12 5 MHz Local Byte Clock signal (signal provided by the PLAYER A control bit is used to ...
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Signal Descriptions (Continued PHY Interface Codes The DP83256 57 PLAYER device converts the Standard 4B 5B FDDI symbol code to the internal code used at the PHY a Interface The PH DATA Indication table shows ...
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Signal Descriptions (Continued) The Idle and PH Invalid encodings overlap Idle symbols received while the PLAYER Idle Line State (ILS0 are not considered PH INVALID) Idle symbols received while the PLAYER than ALS or ILS are treated as ...
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Signal Descriptions (Continued EXTERNAL MATCHING INTERFACE The External Matching Interface provides the means to add external address recognition logic The results of these address comparisons are conveyed on the appropriate signals Symbol Pin I O ECIP ...
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Signal Descriptions (Continued ABus INTERFACE The ABus interface signals provide a 28-bit address 32-bit data bus for transfers between the host system and the MACSI device The ABus uses a bus request bus grant protocol that ...
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Signal Descriptions (Continued) Bus Control Symbol Pin ABus Address Strobe When first asserted this TRI-STATE signals indicates that address valid When this signal is inactive and AB ACK ...
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Signal Descriptions (Continued ELECTRICAL INTERFACE Symbol Pin I O LBC5 3 125 126 I Local Byte Clock 12 5 MHz clocks with duty-cycle generated by the PLAYER device LBC1 127 I Local Byte ...
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Electrical Characteristics 9 1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC DC Input Voltage IN DC Output Voltage OUT T Storage Temperature STG T Lead Temperature L ESD Protection 9 2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter ...
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Electrical Characteristics ELECTRICAL CHARACTERISTICS The AC Electrical characteristics are over the operating range unless otherwise specified AC Characteristics for the Control Bus Interface Symbol Parameter Descriptions T1 CE Setup to LBC T2 LBC Period T3 ...
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Electrical Characteristics FIGURE 9-1 Asynchronous Control Bus Write Cycle Timing FIGURE 9-2 Asynchronous Control Bus Read Cycle Timing (Continued) 141 TL F 11705 – 11705 – 19 ...
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Electrical Characteristics FIGURE 9-3 Control Bus Synchronous Write Cycle Timing FIGURE 9-4 Control Bus Synchronous Read Cycle Timing (Continued) 142 TL F 11705 – 11705 – 21 ...
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Electrical Characteristics AC Characteristics for the Clock Interface Signals Symbol Parameter T51 LBC1 to LBC3 Lead Time T52A LBC1 to LBC5 Lead Time T52B LBC5 Rising to LBC1 Falling Lead Time T53 LBC1 LBC3 and LBC5 Period T54 ...
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... T40 AB ERR AB DEN Hold from AB CLK T41 SIZ DEN Data Valid from AB CLK T42 SIZ DEN Data sustain from AB CLK F1 AB CLK Frequency This specification applies to ‘‘normal’’ ABus Mode only (SIMR1 EAM please contact National Semiconductor (Continued) Min ...
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Electrical Characteristics AC Characteristics for Port A Interface and Port B Interface for MACSI Revision D Symbol Parameter T26 PHY Data Inputs ECIP ECOPY EM EA AFINHIB Setup to LBC1 T27 PHY Data Inputs ECIP ECOPY EM EA ...
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Electrical Characteristics FIGURE 9-7a ABus Read Cycle Timing Diagram (Continued) 146 TL F 11705 – 24 ...
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Electrical Characteristics Figure 9-7b ABus Write Cycle Timing Diagram (Continued) 147 TL F 11705 – 25 ...
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Electrical Characteristics AC Signal Testing Test Conditions for AC Testing (Continued) FIGURE 9-8 AC Signal Testing FIGURE 9-9 ...
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Electrical Characteristics Test Equivalent Loads (Continued 11705– 11705– 30 FIGURE 9-10 Test Equivalent Loads 149 TL F 11705 – 11705 – 11705 – 32 ...
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Pin Table and Pin Diagram Pin Description I O Pin Description AD30 AD29 GND 44 GND ...
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Pin Table and Pin Diagram The pinout of the MACSI device is shown in the diagram below (Continued) FIGURE 10-1 DP83266 Pinout 151 TL F 11705 – 33 ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Quad Flat Pack (VUL) Order Number DP83266VF NS Package Number VUL160A ...