DP83266VF National Semiconductor, DP83266VF Datasheet - Page 51

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

7 0 Control Information
Control Registers
The Control Registers are used to configure and control the
operation of the MACSI device
The Control Registers include the following registers
MAC Mode Registers (MCMR2–0) establish the major
operating parameters for the MAC portion of the MACSI
device
Option Register (Option) selects major configuration
options for the MAC portion of the device
Function Register (Function) initiates major MAC level
functions
MAC Revision (MCRev) this register contains the silicon
revision code for the MAC state machines of this device
System Interface Mode Registers (SIMR1–0) estab-
lishes major operating parameters for the System Inter-
face
Pointer RAM Control and Address Register (PCAR) is
used to program the parameters for the PTOP (Pointer
RAM Operation) service function
Mailbox Address Register (MBAR) is used to program
the memory address of the mailbox used in the data
transfer of the PTOP service function
Limit Address Register (LAR) is used to program the
parameters and data used in the LMOP (Limit RAM Op-
eration) service function
Limit Data Register (LDR) is used to program the data
used in the LMOP service function
(Continued)
FIGURE 7-1 Event Registers Hierarchy
51
Event Registers
The Event Registers record the occurrence of events or
series of events Events are recorded and contribute to gen-
erating Interrupt signals There is a two-level hierarchy in
generating this signal as shown in Figure 7-1
Request Channel 0 Configuration Registers (R0CR1–
0) are used to program the operational parameters for
Request Channel 0
Request Channel 1 Configuration Registers (R1CR1–
0) are used to program the operational parameters for
Request Channel 1
Request Channel 0 Expected Frame Status Register
(R0EFSR) defines the expected frame status for frames
being confirmed on Request Channel 0
Request Channel 1 Expected Frame Status Register
(R1EFSR) defines the expected frame status for frames
being confirmed on Request Channel 1
Indicate Threshold Register (ITR) is used to specify a
maximum number of frames that can be copied onto an
Indicate Channel before a breakpoint is generated
Indicate Mode Configuration Register (IMCR) speci-
fies how the incoming frames are sorted onto Indicate
Channels enables frame filtering and enables break-
points on various burst boundaries
Indicate Copy Configuration Register (ICCR) is used
to program the copy criteria for each of the Indicate
Channels
Indicate Header Length Register (IHLR) defines the
length of the frame header for use with the Header Info
Sort Mode
TL F 11705 – 17