DP83266VF National Semiconductor, DP83266VF Datasheet - Page 90

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
7 0 Control Information
System Interface Mode Register 0 (SIMR0)
The System Interface Mode Register 0 (SIMR0) is used to program major operating parameters for the System Interface of the
MACSI device This register should be programmed only at power-on or after a software Master Reset
This register is cleared upon reset
Access Rules
Register Bits
SMLB
D7
Address
TEST
FABCLK
MRST
FLOW
BIGEND
VIRT
SMLQ
SMLB
Symbol
100h
SMLQ
D6
Test Mode Enables test logic in which the transmitted frames counter will cause a service loss after four
frames instead of 255 frames
Fast ABus Clock For any AB CLK frequency greater than LBC (12 5 MHz) this bit must be zero For an
AB CLK frequency equal to LBC the User may optionally set this bit Setting this bit causes a slight
optimization of the internal MACSI synchronization timing valid only for the case where AB CLK
12 5 MHz National recommends that all users leave this bit as zero
Master Reset When this bit is set the indicate Request and Status Space Machines are placed in Stop
Mode and System Interface registers are initialized to the values shown in Table 7-2 This bit is cleared after
the reset is complete
Flow Parity When this bit is set parity checking is enabled at the MAC Indicate Data (Receive Data)
interface The MACSI device uses Odd parity at all interfaces The System Interface reports parity errors in the
STAR BPE bit (for receive data from the MAC) or the STAR ERR (for descriptor fetch parity errors) Data
parity does not get checked at the ABus Interface When this bit is set the parity bit for each ABus data byte
flows with the data byte through the internal FIFO and across the MAC Request (Transmit) interface where it
is checked by the Ring Engine Good parity is always generated on ABus If this bit is reset good parity is
generated at the MAC Request interface For the MAC Indicate Data interface the parity check includes the
frame’s FC through ED fields When this bit is Zero no parity is checked on the MAC Indicate Data interface
In the BSI device this bit also controlled the Control Bus Parity In the MACSI device Control Bus Parity is
enabled using the MCMode CBP bit (see ‘‘MAC Mode Register 0 (MCMR0)’’)
For systems using parity on the ABus the User must initialize the Receive burst FIFO RAM after reset by
doing a send-to-self of a frame at least 64 bytes in length
Big Endian Data Format Selects between the Little Endian (BIGEND
format See Figure 6-1
Virtual Address Mode Selects between virtual (VIRT
ABus
Small Queue Selects the size of all Descriptor queues and lists When SMLQ
SMLQ
Small Bursts Selects size of bursts on ABus When SMLB
transfers When SMLB
e
Always
Read
VIRT
D5
1 the size is 1 kBytes Note that data pages are always 4 kBytes
BIGEND
(Continued)
D4
e
1 the MACSI device uses 1- and 4-word transfers
Always
Write
FLOW
D3
90
MRST
D2
Description
e
FABCLK
1) or physical (VIRT
D1
e
0 the MACSI device uses 1- 4- and 8-word
TEST
D0
e
0) or Big Endian (BIGEND
e
e
0) address mode on the
0 the size is 4 kBytes when
e
LBC
e
1) data
e